upduino-example/example_vsim.cpp at master · XarkLabs/upduino-example · GitHub

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// C++ "driver" for UPduino example
//
// vim: set et ts=4 sw=4
//

#include<signal.h>
#include<stdio.h>
#include<stdlib.h>
#include<unistd.h>

#include"verilated.h"

#include"Vexample_top.h"

// 1 to save FST waveform trace file
#defineVM_TRACE1

#include"verilated_fst_c.h"// for VM_TRACE

#defineLOGDIR"logs/"

// Current simulation time (64-bit unsigned)
vluint64_t main_time = 0;

volatilebool done;

staticFILE *logfile;
staticchar log_buff[16384];

staticvoidlog_printf(constchar *fmt, ...)
{
 va_list args;
va_start(args, fmt);
vsnprintf(log_buff, sizeof(log_buff), fmt, args);
fputs(log_buff, stdout);
fputs(log_buff, logfile);
va_end(args);
}

staticvoidlogonly_printf(constchar *fmt, ...)
{
 va_list args;
va_start(args, fmt);
vsnprintf(log_buff, sizeof(log_buff), fmt, args);
fputs(log_buff, logfile);
va_end(args);
}

voidctrl_c(int s)
{
 (void)s;
 done = true;
}

// Called by $time in Verilog
doublesc_time_stamp()
{
return main_time;
}

intmain(int argc, char **argv)
{
structsigaction sigIntHandler;

 sigIntHandler.sa_handler = ctrl_c;
sigemptyset(&sigIntHandler.sa_mask);
 sigIntHandler.sa_flags = 0;

sigaction(SIGINT, &sigIntHandler, NULL);

if ((logfile = fopen(LOGDIR"example_vsim.log", "w")) == NULL)
 {
printf("can't create "LOGDIR"example_vsim.log\n");
exit(EXIT_FAILURE);
 }

log_printf("\nSimulation started\n");

Verilated::commandArgs(argc, argv);

#if VM_TRACE
Verilated::traceEverOn(true);
#endif

 Vexample_top *top = new Vexample_top;

#if VM_TRACE
constauto trace_path = LOGDIR"example_vsim.fst";
logonly_printf("Writing FST waveform file to \"%s\"...\n", trace_path);
 VerilatedFstC *tfp = new VerilatedFstC;

 top->trace(tfp, 99); // trace to heirarchal depth of 99
 tfp->open(trace_path);
#endif

while (!done && !Verilated::gotFinish())
 {
 top->gpio_20 = 1; // clock rising
 top->eval();

#if VM_TRACE
 tfp->dump(main_time);
#endif
 main_time++;

 top->gpio_20 = 0; // clock falling
 top->eval();

#if VM_TRACE
 tfp->dump(main_time);
#endif
 main_time++;

if (main_time >= 10000000ull)
 {
 done = true;
 }
 }

 top->final();

#if VM_TRACE
 tfp->close();
#endif

log_printf("Simulation ended after %lu clock ticks\n",
 (main_time / 2));

returnEXIT_SUCCESS;
}