diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index f0359455dc205..41da143c74a52 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -867,6 +867,7 @@ properties: - items: - enum: + - arduino,monza - qcom,monaco-ac-evk - qcom,monaco-evk - qcom,qcs8300-ride diff --git a/Documentation/devicetree/bindings/hwmon/ti,ina2xx.yaml b/Documentation/devicetree/bindings/hwmon/ti,ina2xx.yaml index d3cde89366866..a79ade3142fa4 100644 --- a/Documentation/devicetree/bindings/hwmon/ti,ina2xx.yaml +++ b/Documentation/devicetree/bindings/hwmon/ti,ina2xx.yaml @@ -28,7 +28,9 @@ properties: - ti,ina228 - ti,ina230 - ti,ina231 + - ti,ina232 - ti,ina233 + - ti,ina234 - ti,ina237 - ti,ina238 - ti,ina260 @@ -113,6 +115,8 @@ allOf: - ti,ina228 - ti,ina230 - ti,ina231 + - ti,ina232 + - ti,ina234 - ti,ina237 - ti,ina238 - ti,ina260 @@ -134,6 +138,8 @@ allOf: - ti,ina226 - ti,ina230 - ti,ina231 + - ti,ina232 + - ti,ina234 - ti,ina260 - ti,ina700 - ti,ina780 diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml index e7565592da862..541c1c54ddb0f 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml @@ -15,7 +15,13 @@ description: properties: compatible: - const: qcom,sm8450-lpass-lpi-pinctrl + oneOf: + - const: qcom,sm8450-lpass-lpi-pinctrl + - items: + - enum: + - qcom,qcs8300-lpass-lpi-pinctrl + - qcom,sa8775p-lpass-lpi-pinctrl + - const: qcom,sm8450-lpass-lpi-pinctrl reg: items: diff --git a/Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-ports.yaml b/Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-ports.yaml index 08c618e7e4281..3b03e2acd67e0 100644 --- a/Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-ports.yaml +++ b/Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-ports.yaml @@ -126,13 +126,16 @@ patternProperties: reg: contains: # MI2S DAI ID range PRIMARY_MI2S_RX - QUATERNARY_MI2S_TX and - # QUINARY_MI2S_RX - QUINARY_MI2S_TX + # QUINARY_MI2S_RX - QUINARY_MI2S_TX and + # LPI_MI2S_RX_0 - LPI_MI2S_TX_6 items: oneOf: - minimum: 16 maximum: 23 - minimum: 127 maximum: 128 + - minimum: 137 + maximum: 152 then: required: - qcom,sd-lines diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 7fa32190761b6..5c46fe72204b0 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -154,6 +154,8 @@ patternProperties: description: Arctic Sand "^arcx,.*": description: arcx Inc. / Archronix Inc. + "^arduino,.*": + description: Arduino SRL "^argon40,.*": description: Argon 40 Technologies Limited "^ariaboard,.*": diff --git a/Documentation/hwmon/ina2xx.rst b/Documentation/hwmon/ina2xx.rst index a3860aae444c0..d64e7af46a124 100644 --- a/Documentation/hwmon/ina2xx.rst +++ b/Documentation/hwmon/ina2xx.rst @@ -74,6 +74,16 @@ Supported chips: https://us1.silergy.com/ + * Texas Instruments INA234 + + Prefix: 'ina234' + + Addresses: I2C 0x40 - 0x43 + + Datasheet: Publicly available at the Texas Instruments website + + https://www.ti.com/ + Author: Lothar Felten Description @@ -89,7 +99,7 @@ interface. The INA220 monitors both shunt drop and supply voltage. The INA226 is a current shunt and power monitor with an I2C interface. The INA226 monitors both a shunt voltage drop and bus supply voltage. -INA230 and INA231 are high or low side current shunt and power monitors +INA230, INA231, and INA234 are high or low side current shunt and power monitors with an I2C interface. The chips monitor both a shunt voltage drop and bus supply voltage. @@ -124,8 +134,17 @@ power1_input Power(uW) measurement channel shunt_resistor Shunt resistance(uOhm) channel (not for ina260) ======================= =============================================== -Additional sysfs entries for ina226, ina230, ina231, ina260, and sy24655 ------------------------------------------------------------------------- +Additional sysfs entries +------------------------ + +Additional entries are available for the following chips: + + * ina226 + * ina230 + * ina231 + * ina234 + * ina260 + * sy24655 ======================= ==================================================== curr1_lcrit Critical low current diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 9056576bdf7bc..e44ccfee9b5b1 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -58,6 +58,7 @@ dtb-$(CONFIG_ARCH_QCOM) += lemans-evk-el2.dtb lemans-evk-ifp-mezzanine-dtbs := lemans-evk.dtb lemans-evk-ifp-mezzanine.dtbo dtb-$(CONFIG_ARCH_QCOM) += lemans-evk-ifp-mezzanine.dtb +dtb-$(CONFIG_ARCH_QCOM) += monaco-arduino-monza.dtb dtb-$(CONFIG_ARCH_QCOM) += monaco-ac-evk.dtb dtb-$(CONFIG_ARCH_QCOM) += monaco-evk.dtb diff --git a/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts b/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts new file mode 100644 index 0000000000000..d1346ca5dd4ef --- /dev/null +++ b/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts @@ -0,0 +1,593 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; + +#include +#include +#include +#include + +#include "monaco-monza-som.dtsi" + +/ { + model = "Arduino VENTUNO Q"; + compatible = "arduino,monza", "qcom,qcs8300"; + + aliases { + ethernet0 = ðernet0; + i2c1 = &i2c1; + serial0 = &uart7; + serial1 = &uart10; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&gpio_keys_default>; + pinctrl-names = "default"; + + button-home { + label = "Home Key"; + linux,code = ; + gpios = <&tlmm 79 GPIO_ACTIVE_LOW>; + debounce-interval = <60>; + }; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&adv7535_out>; + }; + }; + }; + + sound { + compatible = "qcom,qcs8275-sndcard"; + model = "arduino-monza"; + audio-routing = "IN12", "Headset Mic12", + "Headset Mic12", "MICBIAS", + "IN56", "Headset Mic56", + "Headset Mic56", "MICBIAS", + "MIC1", "MICBIAS", + "Headphone", "HPL", + "Headphone", "HPR", + "Receiver", "RCVL", + "Receiver", "RCVR", + "Speaker", "SPKL", + "Speaker", "SPKR"; + + pinctrl-0 = <&quad_mi2s_active>, <&quad_mclk_active>, <&lpi_i2s4_active>; + pinctrl-names = "default"; + + pri-i2s-playback-dai-link { + link-name = "Analog Playback"; + + codec { + sound-dai = <&max98091>; + }; + + cpu { + sound-dai = <&q6apmbedai 137>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + pri-i2s-capture-dai-link { + link-name = "Analog Capture"; + + codec { + sound-dai = <&max98091>; + }; + + cpu { + sound-dai = <&q6apmbedai 138>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + hdmi-mi2s-playback-dai-link { + link-name = "HDMI Playback"; + + codec { + sound-dai = <&adv7535>; + }; + + cpu { + sound-dai = <&q6apmbedai 145>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + displayport-0-dai-link { + link-name = "DisplayPort0 Playback"; + + codec { + sound-dai = <&mdss_dp0>; + }; + + cpu { + sound-dai = <&q6apmbedai DISPLAY_PORT_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + }; + + vdc_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vdc_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vdc_1v8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vdc_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vdc_5v: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "vdc_5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&tlmm 49 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + startup-delay-us = <20000>; + }; + + vreg_nvme: regulator-3p3-m2 { + compatible = "regulator-fixed"; + regulator-name = "vreg_m2_3p3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&tlmm 51 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <20000>; + }; +}; + +&cci1 { + status = "okay"; +}; + +&cci1_i2c1 { + fan_controller: fan-controller@2f { + compatible = "microchip,emc2305"; + reg = <0x2f>; + #address-cells = <1>; + #size-cells = <0>; + #pwm-cells = <3>; + + fan: fan@0 { + reg = <0x0>; + pwms = <&fan_controller 26000 PWM_POLARITY_INVERTED 1>; + #cooling-cells = <2>; + }; + }; +}; + +ðernet0 { + phy-mode = "2500base-x"; + phy-handle = <&hsgmii_phy0>; + + pinctrl-0 = <ðernet0_default>; + pinctrl-names = "default"; + + snps,mtl-rx-config = <&mtl_rx_setup>; + snps,mtl-tx-config = <&mtl_tx_setup>; + + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + hsgmii_phy0: ethernet-phy@1c { + compatible = "ethernet-phy-id004d.d101"; + reg = <0x1c>; + reset-gpios = <&tlmm 50 GPIO_ACTIVE_LOW>; + reset-assert-us = <11000>; + reset-deassert-us = <70000>; + }; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <4>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + snps,route-up; + snps,priority = <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x1>; + snps,route-ptp; + }; + + queue2 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x2>; + snps,route-avcp; + }; + + queue3 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x3>; + snps,priority = <0xc>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <4>; + + queue0 { + snps,dcb-algorithm; + }; + + queue1 { + snps,dcb-algorithm; + }; + + queue2 { + snps,avb-algorithm; + snps,send_slope = <0x1000>; + snps,idle_slope = <0x1000>; + snps,high_credit = <0x3e800>; + snps,low_credit = <0xffc18000>; + }; + + queue3 { + snps,avb-algorithm; + snps,send_slope = <0x1000>; + snps,idle_slope = <0x1000>; + snps,high_credit = <0x3e800>; + snps,low_credit = <0xffc18000>; + }; + }; +}; + +&i2c12 { + clock-frequency = <400000>; + + status = "okay"; + + typec@8 { + compatible = "cypress,cypd4226"; + reg = <0x08>; + pinctrl-0 = <&typec_default_state>; + pinctrl-names = "default"; + interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>; + + #address-cells = <1>; + #size-cells = <0>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + ucsi_hs_ccg_p0: endpoint { + remote-endpoint = <&usb_1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + ucsi_ss_ccg_p0: endpoint { + remote-endpoint = <&usb_1_dwc3_ss>; + }; + }; + }; + }; + }; + + max98091: audio-codec@10 { + compatible = "maxim,max98091"; + reg = <0x10>; + pinctrl-0 = <&max98091_default>; + pinctrl-names = "default"; + interrupts-extended = <&tlmm 16 IRQ_TYPE_LEVEL_HIGH>; /* GPIO_16 */ + clocks = <&q6prmcc LPASS_CLK_ID_MCLK_3 LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "mclk"; + #sound-dai-cells = <0>; + }; + + adv7535: bridge@3d { + compatible = "adi,adv7535"; + reg = <0x3d>; + pinctrl-0 = <&adv7535_default>; + pinctrl-names = "default"; + interrupts-extended = <&tlmm 93 IRQ_TYPE_EDGE_FALLING>; + avdd-supply = <&vdc_1v8>; + dvdd-supply = <&vdc_1v8>; + pvdd-supply = <&vdc_1v8>; + a2vdd-supply = <&vdc_1v8>; + v3p3-supply = <&vdc_3v3>; + v1p2-supply = <&vdc_1v8>; + adi,dsi-lanes = <4>; + #sound-dai-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7535_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + adv7535_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; + + power-sensor@40 { + compatible = "ti,ina232"; + reg = <0x40>; + shunt-resistor = <2000>; + }; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dp0 { + status = "okay"; +}; + +&mdss_dp0_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp0_phy { + status = "okay"; +}; + +&mdss_dsi0 { + status = "okay"; +}; + +&mdss_dsi0_out { + remote-endpoint = <&adv7535_in>; + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi0_phy { + status = "okay"; +}; + +&pcie0 { + pinctrl-0 = <&pcie0_default_state>; + pinctrl-names = "default"; + + vddpe-3v3-supply = <&vdc_3v3>; +}; + +&pcie1 { + pinctrl-0 = <&pcie1_default_state>; + pinctrl-names = "default"; + + vddpe-3v3-supply = <&vreg_nvme>; +}; + +&pcieport0 { + reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; + + pci@0,0 { + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x01 0xff>; + ranges; + reg = <0x010000 0x00 0x00 0x00 0x00>; + + pci@2,0 { + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x00 0xff>; + ranges; + reg = <0x021000 0x00 0x00 0x00 0x00>; + + usb@0 { + compatible = "pci104c,8241"; + reg = <0 0 0 0 0>; + ti,pwron-active-high; + }; + }; + }; +}; + +&pcieport1 { + reset-gpios = <&tlmm 23 GPIO_ACTIVE_LOW>; +}; + +&thermal_zones { + cpuss-0-0-thermal { + polling-delay = <2000>; + + trips { + cpuss0_active: cpuss-active { + temperature = <32000>; + hysteresis = <2000>; + type = "active"; + }; + }; + + cooling-maps { + map-active { + trip = <&cpuss0_active>; + cooling-device = <&fan 0 THERMAL_NO_LIMIT>; + }; + }; + }; +}; + +&tlmm { + pcie0_default_state: pcie0-default-state { + wake-pins { + pins = "gpio0"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + clkreq-pins { + pins = "gpio1"; + function = "pcie0_clkreq"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-pins { + pins = "gpio2"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + typec_default_state: typec-default-state { + pins = "gpio3"; + function = "gpio"; + bias-disable; + }; + + ethernet0_default: ethernet0-default-state { + ethernet0_mdc: ethernet0-mdc-pins { + pins = "gpio5"; + function = "emac0_mdc"; + drive-strength = <16>; + bias-pull-up; + }; + + ethernet0_mdio: ethernet0-mdio-pins { + pins = "gpio6"; + function = "emac0_mdio"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + max98091_default: max98091-default-state { + pins = "gpio16"; + function = "gpio"; + bias-pull-up; + }; + + pcie1_default_state: pcie1-default-state { + wake-pins { + pins = "gpio21"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + clkreq-pins { + pins = "gpio22"; + function = "pcie1_clkreq"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-pins { + pins = "gpio23"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + gpio_keys_default: gpio-keys-default-state { + pins = "gpio79"; + function = "gpio"; + bias-disable; + }; + + adv7535_default: adv7535-default-state { + pins = "gpio93"; + function = "gpio"; + bias-pull-up; + }; +}; + +&uart7 { + status = "okay"; +}; + +&uart10 { + status = "okay"; + + bluetooth: bluetooth { + compatible = "qcom,qca2066-bt"; + enable-gpios = <&tlmm 55 GPIO_ACTIVE_HIGH>; + clocks = <&sleep_clk>; + }; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3_hs { + remote-endpoint = <&ucsi_hs_ccg_p0>; +}; + +&usb_1_dwc3_ss { + remote-endpoint = <&ucsi_ss_ccg_p0>; +}; + +/* Internally connected to the MCU (e.g. for DFU). */ +&usb_2 { + dr_mode = "host"; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/monaco-evk-ifp-mezzanine.dtso b/arch/arm64/boot/dts/qcom/monaco-evk-ifp-mezzanine.dtso index e6beb4393430b..a6e57ec8a1e14 100644 --- a/arch/arm64/boot/dts/qcom/monaco-evk-ifp-mezzanine.dtso +++ b/arch/arm64/boot/dts/qcom/monaco-evk-ifp-mezzanine.dtso @@ -50,15 +50,15 @@ }; &pcie0 { - iommu-map = <0x0 &pcie_smmu 0x0 0x1>, - <0x100 &pcie_smmu 0x1 0x1>, - <0x208 &pcie_smmu 0x2 0x1>, - <0x210 &pcie_smmu 0x3 0x1>, - <0x218 &pcie_smmu 0x4 0x1>, - <0x300 &pcie_smmu 0x5 0x1>, - <0x400 &pcie_smmu 0x6 0x1>, - <0x500 &pcie_smmu 0x7 0x1>, - <0x501 &pcie_smmu 0x8 0x1>; + iommu-map = <0x0 &pcie_smmu 0x0 0x0 0x1>, + <0x100 &pcie_smmu 0x1 0x0 0x1>, + <0x208 &pcie_smmu 0x2 0x0 0x1>, + <0x210 &pcie_smmu 0x3 0x0 0x1>, + <0x218 &pcie_smmu 0x4 0x0 0x1>, + <0x300 &pcie_smmu 0x5 0x0 0x1>, + <0x400 &pcie_smmu 0x6 0x0 0x1>, + <0x500 &pcie_smmu 0x7 0x0 0x1>, + <0x501 &pcie_smmu 0x8 0x0 0x1>; }; &pcieport0 { diff --git a/arch/arm64/boot/dts/qcom/monaco-monza-som.dtsi b/arch/arm64/boot/dts/qcom/monaco-monza-som.dtsi new file mode 100644 index 0000000000000..36af1ad2105d5 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/monaco-monza-som.dtsi @@ -0,0 +1,323 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include + +#include "monaco.dtsi" +#include "monaco-pmics.dtsi" + +/ { + /* This comes from a PMIC handled within the SAIL domain */ + vreg_s2s: vreg-s2s { + compatible = "regulator-fixed"; + regulator-name = "vreg_s2s"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pmm8654au-rpmh-regulators"; + qcom,pmic-id = "a"; + + vreg_l3a: ldo3 { + regulator-name = "vreg_l3a"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + regulator-always-on; + }; + + vreg_l4a: ldo4 { + regulator-name = "vreg_l4a"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l5a: ldo5 { + regulator-name = "vreg_l5a"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l6a: ldo6 { + regulator-name = "vreg_l6a"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l7a: ldo7 { + regulator-name = "vreg_l7a"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l8a: ldo8 { + regulator-name = "vreg_l8a"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l9a: ldo9 { + regulator-name = "vreg_l9a"; + regulator-min-microvolt = <2970000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + }; + + regulators-1 { + compatible = "qcom,pmm8654au-rpmh-regulators"; + qcom,pmic-id = "c"; + + vreg_s5c: smps5 { /* LPDDR VDD2H */ + regulator-name = "vreg_s5c"; + regulator-min-microvolt = <1104000>; + regulator-max-microvolt = <1104000>; + regulator-initial-mode = ; + }; + + vreg_l1c: ldo1 { /* LPDDR VDDQ */ + regulator-name = "vreg_l1c"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <512000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l2c: ldo2 { /* LPDDR VDD2L */ + regulator-name = "vreg_l2c"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <904000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l4c: ldo4 { + regulator-name = "vreg_l4c"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l7c: ldo7 { + regulator-name = "vreg_l7c"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l8c: ldo8 { /* LPDDR VDD1 */ + regulator-name = "vreg_l8c"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l9c: ldo9 { /* QFPROM */ + regulator-name = "vreg_l9c"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + }; +}; + +&mdss_dp0 { + pinctrl-0 = <&dp_hpd>; + pinctrl-names = "default"; +}; + +&mdss_dp0_phy { + vdda-phy-supply = <&vreg_l5a>; + vdda-pll-supply = <&vreg_l4a>; +}; + +&mdss_dsi0 { + vdda-supply = <&vreg_l5a>; +}; + +&mdss_dsi0_phy { + vdds-supply = <&vreg_l4a>; +}; + +&gpi_dma0 { + status = "okay"; +}; + +&gpi_dma1 { + status = "okay"; +}; + +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/qcs8300/a623_zap.mbn"; +}; + +&iris { + status = "okay"; +}; + +/* PCIe0 Gen4 x2 */ +&pcie0 { + iommu-map = <0x0 &pcie_smmu 0x0000 0x0 0x1>, + <0x100 &pcie_smmu 0x0001 0x0 0x1>, + <0x200 &pcie_smmu 0x0007 0x0 0x1>, + <0x208 &pcie_smmu 0x0002 0x0 0x1>, + <0x210 &pcie_smmu 0x0003 0x0 0x1>, + <0x218 &pcie_smmu 0x0004 0x0 0x1>, + <0x300 &pcie_smmu 0x0005 0x0 0x1>, + <0x400 &pcie_smmu 0x0006 0x0 0x1>; + + status = "okay"; +}; + +&pcie0_phy { + vdda-phy-supply = <&vreg_l6a>; + vdda-pll-supply = <&vreg_l5a>; + + status = "okay"; +}; + +/* PCIe1 Gen4 x4 */ +&pcie1 { + status = "okay"; +}; + +&pcie1_phy { + vdda-phy-supply = <&vreg_l6a>; + vdda-pll-supply = <&vreg_l5a>; + + status = "okay"; +}; + +&qupv3_id_0 { + firmware-name = "qcom/qcs8300/qupv3fw.elf"; + + status = "okay"; +}; + +&qupv3_id_1 { + firmware-name = "qcom/qcs8300/qupv3fw.elf"; + status = "okay"; +}; + +/* There is a HW/FW issue preventing proper REFGEN hardware voting + * for the USB2 HS PHY. As a workaround, we force REFGEN to stay + * always‑on in software, matching initial bootloader config. + */ +&refgen { + regulator-always-on; +}; + +&remoteproc_adsp { + firmware-name = "qcom/qcs8300/adsp.mbn"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/qcs8300/cdsp0.mbn"; + + status = "okay"; +}; + +&remoteproc_gpdsp { + firmware-name = "qcom/qcs8300/gpdsp0.mbn"; + + status = "okay"; +}; + +/* OnSom eMMC */ +&sdhc_1 { + vmmc-supply = <&vreg_l8a>; + vqmmc-supply = <&vreg_s2s>; + + bus-width = <8>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + + no-sd; + no-sdio; + non-removable; + + status = "okay"; +}; + +/* Ethernet/SGMII */ +&serdes0 { + phy-supply = <&vreg_l5a>; + + status = "okay"; +}; + +&tlmm { + dp_hpd: dp-hpd-state { + pins = "gpio94"; + function = "edp0_hot"; + bias-disable; + }; +}; + +/* USB0 HS + SS */ +&usb_1_hsphy { + vdda-pll-supply = <&vreg_l7a>; + vdda18-supply = <&vreg_l7c>; + vdda33-supply = <&vreg_l9a>; + + status = "okay"; +}; + +&usb_qmpphy { + vdda-phy-supply = <&vreg_l7a>; + vdda-pll-supply = <&vreg_l5a>; + + status = "okay"; +}; + +/* USB1 HS */ +&usb_2_hsphy { + vdda-pll-supply = <&vreg_l7a>; + vdda18-supply = <&vreg_l7c>; + vdda33-supply = <&vreg_l9a>; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index d944da5238049..92826c08a858d 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -22,6 +22,7 @@ #include #include #include +#include #include / { @@ -2394,8 +2395,8 @@ interconnect-names = "pcie-mem", "cpu-pcie"; - iommu-map = <0x0 &pcie_smmu 0x0000 0x1>, - <0x100 &pcie_smmu 0x0001 0x1>; + iommu-map = <0x0 &pcie_smmu 0x0000 0x0 0x1>, + <0x100 &pcie_smmu 0x0001 0x0 0x1>; resets = <&gcc GCC_PCIE_0_BCR>, <&gcc GCC_PCIE_0_LINK_DOWN_BCR>; @@ -2569,8 +2570,8 @@ &config_noc SLAVE_PCIE_1 QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "pcie-mem", "cpu-pcie"; - iommu-map = <0x0 &pcie_smmu 0x0080 0x1>, - <0x100 &pcie_smmu 0x0081 0x1>; + iommu-map = <0x0 &pcie_smmu 0x0080 0x0 0x1>, + <0x100 &pcie_smmu 0x0081 0x0 0x1>; resets = <&gcc GCC_PCIE_1_BCR>, <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; @@ -2879,6 +2880,75 @@ }; }; + lpass_tlmm: pinctrl@3440000 { + compatible = "qcom,qcs8300-lpass-lpi-pinctrl", "qcom,sm8450-lpass-lpi-pinctrl"; + reg = <0x0 0x03440000 0x0 0x20000>, + <0x0 0x034d0000 0x0 0x10000>; + + clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "core", "audio"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&lpass_tlmm 0 0 23>; + + quad_mclk_active: quad-mclk-state { + clk-pins { + pins = "gpio5"; + function = "ext_mclk1_c"; + drive-strength = <8>; + bias-disable; + }; + }; + + quad_mi2s_active: quad-active-state { + data-pins { + pins = "gpio2", "gpio3"; + function = "qua_mi2s_data"; + drive-strength = <8>; + bias-disable; + }; + + sclk-pins { + pins = "gpio0"; + function = "qua_mi2s_sclk"; + drive-strength = <8>; + bias-disable; + }; + + ws-pins { + pins = "gpio1"; + function = "qua_mi2s_ws"; + drive-strength = <8>; + bias-disable; + }; + }; + + lpi_i2s4_active: lpi_i2s4-active-state { + data0-pins { + pins = "gpio17"; + function = "i2s4_data"; + drive-strength = <8>; + bias-disable; + }; + + clk-pins { + pins = "gpio12"; + function = "i2s4_clk"; + drive-strength = <8>; + bias-disable; + }; + + ws-pins { + pins = "gpio13"; + function = "i2s4_ws"; + drive-strength = <8>; + bias-disable; + }; + }; + }; + lpass_ag_noc: interconnect@3c40000 { compatible = "qcom,qcs8300-lpass-ag-noc"; reg = <0x0 0x03c40000 0x0 0x17200>; @@ -4922,6 +4992,12 @@ status = "disabled"; }; + refgen: regulator@891c000 { + compatible = "qcom,qcs8300-refgen-regulator", + "qcom,sm8250-refgen-regulator"; + reg = <0x0 0x0891c000 0x0 0x84>; + }; + gpu: gpu@3d00000 { compatible = "qcom,adreno-623.0", "qcom,adreno"; reg = <0x0 0x03d00000 0x0 0x40000>, @@ -5252,9 +5328,29 @@ snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; + usb-role-switch; wakeup-source; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_1_dwc3_ss: endpoint { + }; + }; + }; }; usb_2: usb@a400000 { @@ -5431,14 +5527,14 @@ cci0_i2c0: i2c-bus@0 { reg = <0>; - clock-frequency = <1000000>; + clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; }; cci0_i2c1: i2c-bus@1 { reg = <1>; - clock-frequency = <1000000>; + clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; }; @@ -5468,14 +5564,14 @@ cci1_i2c0: i2c-bus@0 { reg = <0>; - clock-frequency = <1000000>; + clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; }; cci1_i2c1: i2c-bus@1 { reg = <1>; - clock-frequency = <1000000>; + clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; }; @@ -5505,14 +5601,14 @@ cci2_i2c0: i2c-bus@0 { reg = <0>; - clock-frequency = <1000000>; + clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; }; cci2_i2c1: i2c-bus@1 { reg = <1>; - clock-frequency = <1000000>; + clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; }; diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index f2d30d8ee4703..0bb70c07bbbc8 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -408,6 +408,7 @@ CONFIG_MARVELL_88Q2XXX_PHY=y CONFIG_MICREL_PHY=y CONFIG_MICROSEMI_PHY=y CONFIG_AT803X_PHY=y +CONFIG_QCA808X_PHY=m CONFIG_REALTEK_PHY=y CONFIG_ROCKCHIP_PHY=y CONFIG_DP83867_PHY=y diff --git a/drivers/clk/qcom/gcc-qcs8300.c b/drivers/clk/qcom/gcc-qcs8300.c index 7a7f4eca40d8d..fe0632687f9f0 100644 --- a/drivers/clk/qcom/gcc-qcs8300.c +++ b/drivers/clk/qcom/gcc-qcs8300.c @@ -3268,7 +3268,7 @@ static struct gdsc gcc_pcie_0_gdsc = { .pd = { .name = "gcc_pcie_0_gdsc", }, - .pwrsts = PWRSTS_OFF_ON, + .pwrsts = PWRSTS_RET_ON, .flags = VOTABLE | RETAIN_FF_ENABLE | POLL_CFG_GDSCR, }; @@ -3282,7 +3282,7 @@ static struct gdsc gcc_pcie_1_gdsc = { .pd = { .name = "gcc_pcie_1_gdsc", }, - .pwrsts = PWRSTS_OFF_ON, + .pwrsts = PWRSTS_RET_ON, .flags = VOTABLE | RETAIN_FF_ENABLE | POLL_CFG_GDSCR, }; diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c index 47dd76acd31e5..6a14700658141 100644 --- a/drivers/cpufreq/cpufreq-dt-platdev.c +++ b/drivers/cpufreq/cpufreq-dt-platdev.c @@ -157,6 +157,7 @@ static const struct of_device_id blocklist[] __initconst = { { .compatible = "qcom,qcm2290", }, { .compatible = "qcom,qcm6490", }, { .compatible = "qcom,qcs404", }, + { .compatible = "qcom,qcs8300", }, { .compatible = "qcom,qdu1000", }, { .compatible = "qcom,sa8155p" }, { .compatible = "qcom,sa8540p" }, diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig index fdb3ecc2bb041..a4d9b213dcf61 100644 --- a/drivers/hwmon/Kconfig +++ b/drivers/hwmon/Kconfig @@ -2281,7 +2281,7 @@ config SENSORS_INA2XX select REGMAP_I2C help If you say yes here you get support for INA219, INA220, INA226, - INA230, INA231, INA260, and SY24655 power monitor chips. + INA230, INA231, INA234, INA260, and SY24655 power monitor chips. The INA2xx driver is configured for the default configuration of the part as described in the datasheet. diff --git a/drivers/hwmon/ina2xx.c b/drivers/hwmon/ina2xx.c index bc3c1f7314b3e..74bc85344d3a3 100644 --- a/drivers/hwmon/ina2xx.c +++ b/drivers/hwmon/ina2xx.c @@ -135,18 +135,28 @@ static const struct regmap_config ina2xx_regmap_config = { .writeable_reg = ina2xx_writeable_reg, }; -enum ina2xx_ids { ina219, ina226, ina260, sy24655 }; +enum ina2xx_ids { + ina219, + ina226, + ina232, + ina234, + ina260, + sy24655 +}; struct ina2xx_config { u16 config_default; bool has_alerts; /* chip supports alerts and limits */ bool has_ishunt; /* chip has internal shunt resistor */ - bool has_power_average; /* chip has internal shunt resistor */ + bool has_power_average; /* chip supports average power */ + bool has_update_interval; int calibration_value; int shunt_div; + int shunt_voltage_shift; int bus_voltage_shift; int bus_voltage_lsb; /* uV */ int power_lsb_factor; + int current_shift; }; struct ina2xx_data { @@ -166,44 +176,84 @@ static const struct ina2xx_config ina2xx_config[] = { .config_default = INA219_CONFIG_DEFAULT, .calibration_value = 4096, .shunt_div = 100, + .shunt_voltage_shift = 0, .bus_voltage_shift = 3, .bus_voltage_lsb = 4000, .power_lsb_factor = 20, .has_alerts = false, .has_ishunt = false, .has_power_average = false, + .current_shift = 0, + .has_update_interval = false, }, [ina226] = { .config_default = INA226_CONFIG_DEFAULT, .calibration_value = 2048, .shunt_div = 400, + .shunt_voltage_shift = 0, .bus_voltage_shift = 0, .bus_voltage_lsb = 1250, .power_lsb_factor = 25, .has_alerts = true, .has_ishunt = false, .has_power_average = false, + .current_shift = 0, + .has_update_interval = true, + }, + [ina234] = { + .config_default = INA226_CONFIG_DEFAULT, + .calibration_value = 2048, + .shunt_div = 25, /* 2.5 µV/LSB raw ADC reading from INA2XX_SHUNT_VOLTAGE */ + .shunt_voltage_shift = 4, + .bus_voltage_shift = 4, + .bus_voltage_lsb = 25600, + .power_lsb_factor = 32, + .has_alerts = true, + .has_ishunt = false, + .has_power_average = false, + .current_shift = 4, + .has_update_interval = true, + }, + [ina232] = { + .config_default = INA226_CONFIG_DEFAULT, + .calibration_value = 2048, + .shunt_div = 400, + .shunt_voltage_shift = 0, + .bus_voltage_shift = 0, + .bus_voltage_lsb = 1600, + .power_lsb_factor = 32, + .has_alerts = true, + .has_ishunt = false, + .has_power_average = false, + .current_shift = 0, + .has_update_interval = true, }, [ina260] = { .config_default = INA260_CONFIG_DEFAULT, .shunt_div = 400, + .shunt_voltage_shift = 0, .bus_voltage_shift = 0, .bus_voltage_lsb = 1250, .power_lsb_factor = 8, .has_alerts = true, .has_ishunt = true, .has_power_average = false, + .current_shift = 0, + .has_update_interval = true, }, [sy24655] = { .config_default = SY24655_CONFIG_DEFAULT, .calibration_value = 4096, .shunt_div = 400, + .shunt_voltage_shift = 0, .bus_voltage_shift = 0, .bus_voltage_lsb = 1250, .power_lsb_factor = 25, .has_alerts = true, .has_ishunt = false, .has_power_average = true, + .current_shift = 0, + .has_update_interval = false, }, }; @@ -256,7 +306,8 @@ static int ina2xx_get_value(struct ina2xx_data *data, u8 reg, switch (reg) { case INA2XX_SHUNT_VOLTAGE: /* signed register */ - val = DIV_ROUND_CLOSEST((s16)regval, data->config->shunt_div); + val = (s16)regval >> data->config->shunt_voltage_shift; + val = DIV_ROUND_CLOSEST(val, data->config->shunt_div); break; case INA2XX_BUS_VOLTAGE: val = (regval >> data->config->bus_voltage_shift) * @@ -268,7 +319,8 @@ static int ina2xx_get_value(struct ina2xx_data *data, u8 reg, break; case INA2XX_CURRENT: /* signed register, result in mA */ - val = (s16)regval * data->current_lsb_uA; + val = ((s16)regval >> data->config->current_shift) * + data->current_lsb_uA; val = DIV_ROUND_CLOSEST(val, 1000); break; case INA2XX_CALIBRATION: @@ -362,6 +414,7 @@ static u16 ina226_alert_to_reg(struct ina2xx_data *data, int reg, long val) case INA2XX_SHUNT_VOLTAGE: val = clamp_val(val, 0, SHRT_MAX * data->config->shunt_div); val *= data->config->shunt_div; + val <<= data->config->shunt_voltage_shift; return clamp_val(val, 0, SHRT_MAX); case INA2XX_BUS_VOLTAGE: val = clamp_val(val, 0, 200000); @@ -376,6 +429,7 @@ static u16 ina226_alert_to_reg(struct ina2xx_data *data, int reg, long val) val = clamp_val(val, INT_MIN / 1000, INT_MAX / 1000); /* signed register, result in mA */ val = DIV_ROUND_CLOSEST(val * 1000, data->current_lsb_uA); + val <<= data->config->current_shift; return clamp_val(val, SHRT_MIN, SHRT_MAX); default: /* programmer goofed */ @@ -713,7 +767,7 @@ static umode_t ina2xx_is_visible(const void *_data, enum hwmon_sensor_types type const struct ina2xx_data *data = _data; bool has_alerts = data->config->has_alerts; bool has_power_average = data->config->has_power_average; - enum ina2xx_ids chip = data->chip; + bool has_update_interval = data->config->has_update_interval; switch (type) { case hwmon_in: @@ -775,7 +829,7 @@ static umode_t ina2xx_is_visible(const void *_data, enum hwmon_sensor_types type case hwmon_chip: switch (attr) { case hwmon_chip_update_interval: - if (chip == ina226 || chip == ina260) + if (has_update_interval) return 0644; break; default: @@ -990,6 +1044,8 @@ static const struct i2c_device_id ina2xx_id[] = { { "ina226", ina226 }, { "ina230", ina226 }, { "ina231", ina226 }, + { "ina232", ina232 }, + { "ina234", ina234 }, { "ina260", ina260 }, { "sy24655", sy24655 }, { } @@ -1021,6 +1077,14 @@ static const struct of_device_id __maybe_unused ina2xx_of_match[] = { .compatible = "ti,ina231", .data = (void *)ina226 }, + { + .compatible = "ti,ina232", + .data = (void *)ina232 + }, + { + .compatible = "ti,ina234", + .data = (void *)ina234 + }, { .compatible = "ti,ina260", .data = (void *)ina260 diff --git a/include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h b/include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h index 41bc1559cf187..c79d6dc37a5ee 100644 --- a/include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h +++ b/include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h @@ -140,6 +140,22 @@ #define DISPLAY_PORT_RX_6 134 #define DISPLAY_PORT_RX_7 135 #define USB_RX 136 +#define LPI_MI2S_RX_0 137 +#define LPI_MI2S_TX_0 138 +#define LPI_MI2S_RX_1 139 +#define LPI_MI2S_TX_1 140 +#define LPI_MI2S_RX_2 141 +#define LPI_MI2S_TX_2 142 +#define LPI_MI2S_RX_3 143 +#define LPI_MI2S_TX_3 144 +#define LPI_MI2S_RX_4 145 +#define LPI_MI2S_TX_4 146 +#define SENARY_MI2S_RX 147 +#define SENARY_MI2S_TX 148 +#define LPI_MI2S_RX_5 149 +#define LPI_MI2S_TX_5 150 +#define LPI_MI2S_RX_6 151 +#define LPI_MI2S_TX_6 152 #define LPASS_CLK_ID_PRI_MI2S_IBIT 1 #define LPASS_CLK_ID_PRI_MI2S_EBIT 2 diff --git a/sound/soc/qcom/common.c b/sound/soc/qcom/common.c index df5c7048fcc3e..fced8eb951c2d 100644 --- a/sound/soc/qcom/common.c +++ b/sound/soc/qcom/common.c @@ -319,6 +319,12 @@ int qcom_snd_parse_of(struct snd_soc_card *card) link->id = args.args[0]; + if (link->id >= LPASS_MAX_PORT) { + dev_err(dev, "%s: Invalid cpu dai id %d\n", link->name, link->id); + ret = -EINVAL; + goto err; + } + if (platform) { link->platforms->of_node = of_parse_phandle(platform, "sound-dai", diff --git a/sound/soc/qcom/common.h b/sound/soc/qcom/common.h index b7d6f617660ed..f8cc3079b8917 100644 --- a/sound/soc/qcom/common.h +++ b/sound/soc/qcom/common.h @@ -4,8 +4,11 @@ #ifndef __QCOM_SND_COMMON_H__ #define __QCOM_SND_COMMON_H__ +#include #include +#define LPASS_MAX_PORT (LPI_MI2S_TX_6 + 1) + struct qcom_snd_tdm_slot_cfg { unsigned int tx_mask; unsigned int rx_mask; diff --git a/sound/soc/qcom/lpass.h b/sound/soc/qcom/lpass.h index de3ec6f594c11..68b71039b9814 100644 --- a/sound/soc/qcom/lpass.h +++ b/sound/soc/qcom/lpass.h @@ -14,10 +14,11 @@ #include #include #include +#include "common.h" #include "lpass-hdmi.h" #define LPASS_AHBIX_CLOCK_FREQUENCY 131072000 -#define LPASS_MAX_PORTS (DISPLAY_PORT_RX_7 + 1) +#define LPASS_MAX_PORTS (LPASS_MAX_PORT) #define LPASS_MAX_MI2S_PORTS (8) #define LPASS_MAX_DMA_CHANNELS (8) #define LPASS_MAX_HDMI_DMA_CHANNELS (4) diff --git a/sound/soc/qcom/qdsp6/q6afe-dai.c b/sound/soc/qcom/qdsp6/q6afe-dai.c index 0f47aadaabe17..c2a3e17caab52 100644 --- a/sound/soc/qcom/qdsp6/q6afe-dai.c +++ b/sound/soc/qcom/qdsp6/q6afe-dai.c @@ -411,6 +411,8 @@ static int q6afe_dai_prepare(struct snd_pcm_substream *substream, break; case QUINARY_MI2S_RX ... QUINARY_MI2S_TX: case PRIMARY_MI2S_RX ... QUATERNARY_MI2S_TX: + case LPI_MI2S_RX_0 ... LPI_MI2S_TX_4: + case LPI_MI2S_RX_5 ... LPI_MI2S_TX_6: rc = q6afe_i2s_port_prepare(dai_data->port[dai->id], &dai_data->port_config[dai->id].i2s_cfg); if (rc < 0) { @@ -662,6 +664,21 @@ static const struct snd_soc_dapm_route q6afe_dapm_routes[] = { /* USB playback AFE port receives data for playback, hence use the RX port */ {"USB Playback", NULL, "USB_RX"}, + + {"LPI RX0 MI2S Playback", NULL, "LPI_MI2S_RX_0"}, + {"LPI_MI2S_TX_0", NULL, "LPI TX0 MI2S Capture"}, + {"LPI RX1 MI2S Playback", NULL, "LPI_MI2S_RX_1"}, + {"LPI_MI2S_TX_1", NULL, "LPI TX1 MI2S Capture"}, + {"LPI RX2 MI2S Playback", NULL, "LPI_MI2S_RX_2"}, + {"LPI_MI2S_TX_2", NULL, "LPI TX2 MI2S Capture"}, + {"LPI RX3 MI2S Playback", NULL, "LPI_MI2S_RX_3"}, + {"LPI_MI2S_TX_3", NULL, "LPI TX3 MI2S Capture"}, + {"LPI RX4 MI2S Playback", NULL, "LPI_MI2S_RX_4"}, + {"LPI_MI2S_TX_4", NULL, "LPI TX4 MI2S Capture"}, + {"LPI RX5 MI2S Playback", NULL, "LPI_MI2S_RX_5"}, + {"LPI_MI2S_TX_5", NULL, "LPI TX5 MI2S Capture"}, + {"LPI RX6 MI2S Playback", NULL, "LPI_MI2S_RX_6"}, + {"LPI_MI2S_TX_6", NULL, "LPI TX6 MI2S Capture"}, }; static int msm_dai_q6_dai_probe(struct snd_soc_dai *dai) @@ -1006,6 +1023,35 @@ static const struct snd_soc_dapm_widget q6afe_dai_widgets[] = { 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_IN("USB_RX", NULL, 0, SND_SOC_NOPM, 0, 0), + + SND_SOC_DAPM_AIF_IN("LPI_MI2S_RX_0", NULL, + 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_OUT("LPI_MI2S_TX_0", NULL, + 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_IN("LPI_MI2S_RX_1", NULL, + 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_OUT("LPI_MI2S_TX_1", NULL, + 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_IN("LPI_MI2S_RX_2", NULL, + 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_OUT("LPI_MI2S_TX_2", NULL, + 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_IN("LPI_MI2S_RX_3", NULL, + 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_OUT("LPI_MI2S_TX_3", NULL, + 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_IN("LPI_MI2S_RX_4", NULL, + 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_OUT("LPI_MI2S_TX_4", NULL, + 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_IN("LPI_MI2S_RX_5", NULL, + 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_OUT("LPI_MI2S_TX_5", NULL, + 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_IN("LPI_MI2S_RX_6", NULL, + 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_OUT("LPI_MI2S_TX_6", NULL, + 0, SND_SOC_NOPM, 0, 0), }; static const struct snd_soc_component_driver q6afe_dai_component = { @@ -1039,6 +1085,8 @@ static void of_q6afe_parse_dai_data(struct device *dev, /* MI2S specific properties */ case QUINARY_MI2S_RX ... QUINARY_MI2S_TX: case PRIMARY_MI2S_RX ... QUATERNARY_MI2S_TX: + case LPI_MI2S_RX_0 ... LPI_MI2S_TX_4: + case LPI_MI2S_RX_5 ... LPI_MI2S_TX_6: priv = &data->priv[id]; ret = of_property_read_variable_u32_array(node, "qcom,sd-lines", diff --git a/sound/soc/qcom/qdsp6/q6afe.c b/sound/soc/qcom/qdsp6/q6afe.c index 7b59d514b432a..98fc8c33b30e2 100644 --- a/sound/soc/qcom/qdsp6/q6afe.c +++ b/sound/soc/qcom/qdsp6/q6afe.c @@ -130,6 +130,20 @@ #define AFE_PORT_ID_QUATERNARY_MI2S_TX 0x1007 #define AFE_PORT_ID_QUINARY_MI2S_RX 0x1016 #define AFE_PORT_ID_QUINARY_MI2S_TX 0x1017 +#define AFE_PORT_ID_INT0_MI2S_RX 0x102e +#define AFE_PORT_ID_INT0_MI2S_TX 0x102f +#define AFE_PORT_ID_INT1_MI2S_RX 0x1030 +#define AFE_PORT_ID_INT1_MI2S_TX 0x1031 +#define AFE_PORT_ID_INT2_MI2S_RX 0x1032 +#define AFE_PORT_ID_INT2_MI2S_TX 0x1033 +#define AFE_PORT_ID_INT3_MI2S_RX 0x1034 +#define AFE_PORT_ID_INT3_MI2S_TX 0x1035 +#define AFE_PORT_ID_INT4_MI2S_RX 0x1036 +#define AFE_PORT_ID_INT4_MI2S_TX 0x1037 +#define AFE_PORT_ID_INT5_MI2S_RX 0x1038 +#define AFE_PORT_ID_INT5_MI2S_TX 0x1039 +#define AFE_PORT_ID_INT6_MI2S_RX 0x103a +#define AFE_PORT_ID_INT6_MI2S_TX 0x103b /* Start of the range of port IDs for TDM devices. */ #define AFE_PORT_ID_TDM_PORT_RANGE_START 0x9000 @@ -925,6 +939,34 @@ static struct afe_port_map port_maps[AFE_PORT_MAX] = { [RX_CODEC_DMA_RX_7] = { AFE_PORT_ID_RX_CODEC_DMA_RX_7, RX_CODEC_DMA_RX_7, 1, 1}, [USB_RX] = { AFE_PORT_ID_USB_RX, USB_RX, 1, 1}, + [LPI_MI2S_RX_0] = { AFE_PORT_ID_INT0_MI2S_RX, + LPI_MI2S_RX_0, 1, 1}, + [LPI_MI2S_TX_0] = { AFE_PORT_ID_INT0_MI2S_TX, + LPI_MI2S_TX_0, 0, 1}, + [LPI_MI2S_RX_1] = { AFE_PORT_ID_INT1_MI2S_RX, + LPI_MI2S_RX_1, 1, 1}, + [LPI_MI2S_TX_1] = { AFE_PORT_ID_INT1_MI2S_TX, + LPI_MI2S_TX_1, 0, 1}, + [LPI_MI2S_RX_2] = { AFE_PORT_ID_INT2_MI2S_RX, + LPI_MI2S_RX_2, 1, 1}, + [LPI_MI2S_TX_2] = { AFE_PORT_ID_INT2_MI2S_TX, + LPI_MI2S_TX_2, 0, 1}, + [LPI_MI2S_RX_3] = { AFE_PORT_ID_INT3_MI2S_RX, + LPI_MI2S_RX_3, 1, 1}, + [LPI_MI2S_TX_3] = { AFE_PORT_ID_INT3_MI2S_TX, + LPI_MI2S_TX_3, 0, 1}, + [LPI_MI2S_RX_4] = { AFE_PORT_ID_INT4_MI2S_RX, + LPI_MI2S_RX_4, 1, 1}, + [LPI_MI2S_TX_4] = { AFE_PORT_ID_INT4_MI2S_TX, + LPI_MI2S_TX_4, 0, 1}, + [LPI_MI2S_RX_5] = { AFE_PORT_ID_INT5_MI2S_RX, + LPI_MI2S_RX_5, 1, 1}, + [LPI_MI2S_TX_5] = { AFE_PORT_ID_INT5_MI2S_TX, + LPI_MI2S_TX_5, 0, 1}, + [LPI_MI2S_RX_6] = { AFE_PORT_ID_INT6_MI2S_RX, + LPI_MI2S_RX_6, 1, 1}, + [LPI_MI2S_TX_6] = { AFE_PORT_ID_INT6_MI2S_TX, + LPI_MI2S_TX_6, 0, 1}, }; static void q6afe_port_free(struct kref *ref) @@ -1790,6 +1832,20 @@ struct q6afe_port *q6afe_port_get_from_id(struct device *dev, int id) case AFE_PORT_ID_QUATERNARY_MI2S_TX: case AFE_PORT_ID_QUINARY_MI2S_RX: case AFE_PORT_ID_QUINARY_MI2S_TX: + case AFE_PORT_ID_INT0_MI2S_RX: + case AFE_PORT_ID_INT0_MI2S_TX: + case AFE_PORT_ID_INT1_MI2S_RX: + case AFE_PORT_ID_INT1_MI2S_TX: + case AFE_PORT_ID_INT2_MI2S_RX: + case AFE_PORT_ID_INT2_MI2S_TX: + case AFE_PORT_ID_INT3_MI2S_RX: + case AFE_PORT_ID_INT3_MI2S_TX: + case AFE_PORT_ID_INT4_MI2S_RX: + case AFE_PORT_ID_INT4_MI2S_TX: + case AFE_PORT_ID_INT5_MI2S_RX: + case AFE_PORT_ID_INT5_MI2S_TX: + case AFE_PORT_ID_INT6_MI2S_RX: + case AFE_PORT_ID_INT6_MI2S_TX: cfg_type = AFE_PARAM_ID_I2S_CONFIG; break; case AFE_PORT_ID_PRIMARY_TDM_RX ... AFE_PORT_ID_QUINARY_TDM_TX_7: diff --git a/sound/soc/qcom/qdsp6/q6afe.h b/sound/soc/qcom/qdsp6/q6afe.h index a29abe4ce4368..0b8c3ec1315ca 100644 --- a/sound/soc/qcom/qdsp6/q6afe.h +++ b/sound/soc/qcom/qdsp6/q6afe.h @@ -2,8 +2,9 @@ #ifndef __Q6AFE_H__ #define __Q6AFE_H__ +#include "../common.h" -#define AFE_PORT_MAX 137 +#define AFE_PORT_MAX (LPASS_MAX_PORT) #define MSM_AFE_PORT_TYPE_RX 0 #define MSM_AFE_PORT_TYPE_TX 1 diff --git a/sound/soc/qcom/qdsp6/q6apm.h b/sound/soc/qcom/qdsp6/q6apm.h index bfb6167eba78f..f46b5e9a003a8 100644 --- a/sound/soc/qcom/qdsp6/q6apm.h +++ b/sound/soc/qcom/qdsp6/q6apm.h @@ -14,9 +14,10 @@ #include #include #include +#include "../common.h" #include "audioreach.h" -#define APM_PORT_MAX 127 +#define APM_PORT_MAX LPASS_MAX_PORT #define APM_PORT_MAX_AUDIO_CHAN_CNT 8 #define PCM_CHANNEL_NULL 0 #define PCM_CHANNEL_FL 1 /* Front left channel. */ diff --git a/sound/soc/qcom/qdsp6/q6dsp-lpass-ports.c b/sound/soc/qcom/qdsp6/q6dsp-lpass-ports.c index 8542e620ee02d..cc247a0813a20 100644 --- a/sound/soc/qcom/qdsp6/q6dsp-lpass-ports.c +++ b/sound/soc/qcom/qdsp6/q6dsp-lpass-ports.c @@ -88,6 +88,42 @@ .id = did, \ } +#define Q6AFE_MI2S_RX_DAI(pre, did) { \ + .playback = { \ + .stream_name = pre" MI2S Playback", \ + .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ + SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\ + SNDRV_PCM_RATE_176400, \ + .formats = SNDRV_PCM_FMTBIT_S16_LE | \ + SNDRV_PCM_FMTBIT_S24_LE | \ + SNDRV_PCM_FMTBIT_S32_LE, \ + .channels_min = 1, \ + .channels_max = 8, \ + .rate_min = 8000, \ + .rate_max = 176400, \ + }, \ + .name = #did, \ + .id = did, \ + } + +#define Q6AFE_MI2S_TX_DAI(pre, did) { \ + .capture = { \ + .stream_name = pre" MI2S Capture", \ + .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ + SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\ + SNDRV_PCM_RATE_176400, \ + .formats = SNDRV_PCM_FMTBIT_S16_LE | \ + SNDRV_PCM_FMTBIT_S24_LE | \ + SNDRV_PCM_FMTBIT_S32_LE, \ + .channels_min = 1, \ + .channels_max = 8, \ + .rate_min = 8000, \ + .rate_max = 176400, \ + }, \ + .name = #did, \ + .id = did, \ + } + static struct snd_soc_dai_driver q6dsp_audio_fe_dais[] = { { .playback = { @@ -480,6 +516,20 @@ static struct snd_soc_dai_driver q6dsp_audio_fe_dais[] = { .id = QUINARY_MI2S_TX, .name = "QUIN_MI2S_TX", }, + Q6AFE_MI2S_RX_DAI("LPI RX0", LPI_MI2S_RX_0), + Q6AFE_MI2S_RX_DAI("LPI RX1", LPI_MI2S_RX_1), + Q6AFE_MI2S_RX_DAI("LPI RX2", LPI_MI2S_RX_2), + Q6AFE_MI2S_RX_DAI("LPI RX3", LPI_MI2S_RX_3), + Q6AFE_MI2S_RX_DAI("LPI RX4", LPI_MI2S_RX_4), + Q6AFE_MI2S_RX_DAI("LPI RX5", LPI_MI2S_RX_5), + Q6AFE_MI2S_RX_DAI("LPI RX6", LPI_MI2S_RX_6), + Q6AFE_MI2S_TX_DAI("LPI TX0", LPI_MI2S_TX_0), + Q6AFE_MI2S_TX_DAI("LPI TX1", LPI_MI2S_TX_1), + Q6AFE_MI2S_TX_DAI("LPI TX2", LPI_MI2S_TX_2), + Q6AFE_MI2S_TX_DAI("LPI TX3", LPI_MI2S_TX_3), + Q6AFE_MI2S_TX_DAI("LPI TX4", LPI_MI2S_TX_4), + Q6AFE_MI2S_TX_DAI("LPI TX5", LPI_MI2S_TX_5), + Q6AFE_MI2S_TX_DAI("LPI TX6", LPI_MI2S_TX_6), Q6AFE_TDM_PB_DAI("Primary", 0, PRIMARY_TDM_RX_0), Q6AFE_TDM_PB_DAI("Primary", 1, PRIMARY_TDM_RX_1), Q6AFE_TDM_PB_DAI("Primary", 2, PRIMARY_TDM_RX_2), @@ -632,6 +682,8 @@ struct snd_soc_dai_driver *q6dsp_audio_ports_set_config(struct device *dev, break; case QUINARY_MI2S_RX ... QUINARY_MI2S_TX: case PRIMARY_MI2S_RX ... QUATERNARY_MI2S_TX: + case LPI_MI2S_RX_0 ... LPI_MI2S_TX_4: + case LPI_MI2S_RX_5 ... LPI_MI2S_TX_6: q6dsp_audio_fe_dais[i].ops = cfg->q6i2s_ops; break; case PRIMARY_TDM_RX_0 ... QUINARY_TDM_TX_7: diff --git a/sound/soc/qcom/qdsp6/q6routing.c b/sound/soc/qcom/qdsp6/q6routing.c index f49243daa517f..db5f156469c22 100644 --- a/sound/soc/qcom/qdsp6/q6routing.c +++ b/sound/soc/qcom/qdsp6/q6routing.c @@ -127,7 +127,14 @@ { mix_name, "TX_CODEC_DMA_TX_2", "TX_CODEC_DMA_TX_2"}, \ { mix_name, "TX_CODEC_DMA_TX_3", "TX_CODEC_DMA_TX_3"}, \ { mix_name, "TX_CODEC_DMA_TX_4", "TX_CODEC_DMA_TX_4"}, \ - { mix_name, "TX_CODEC_DMA_TX_5", "TX_CODEC_DMA_TX_5"} + { mix_name, "TX_CODEC_DMA_TX_5", "TX_CODEC_DMA_TX_5"}, \ + { mix_name, "LPI_MI2S_TX_0", "LPI_MI2S_TX_0" }, \ + { mix_name, "LPI_MI2S_TX_1", "LPI_MI2S_TX_1" }, \ + { mix_name, "LPI_MI2S_TX_2", "LPI_MI2S_TX_2" }, \ + { mix_name, "LPI_MI2S_TX_3", "LPI_MI2S_TX_3" }, \ + { mix_name, "LPI_MI2S_TX_4", "LPI_MI2S_TX_4" }, \ + { mix_name, "LPI_MI2S_TX_5", "LPI_MI2S_TX_5" }, \ + { mix_name, "LPI_MI2S_TX_6", "LPI_MI2S_TX_6" } #define Q6ROUTING_TX_MIXERS(id) \ SOC_SINGLE_EXT("PRI_MI2S_TX", PRIMARY_MI2S_TX, \ @@ -320,6 +327,27 @@ id, 1, 0, msm_routing_get_audio_mixer, \ msm_routing_put_audio_mixer), \ SOC_SINGLE_EXT("TX_CODEC_DMA_TX_5", TX_CODEC_DMA_TX_5, \ + id, 1, 0, msm_routing_get_audio_mixer, \ + msm_routing_put_audio_mixer), \ + SOC_SINGLE_EXT("LPI_MI2S_TX_0", LPI_MI2S_TX_0, \ + id, 1, 0, msm_routing_get_audio_mixer, \ + msm_routing_put_audio_mixer), \ + SOC_SINGLE_EXT("LPI_MI2S_TX_1", LPI_MI2S_TX_1, \ + id, 1, 0, msm_routing_get_audio_mixer, \ + msm_routing_put_audio_mixer), \ + SOC_SINGLE_EXT("LPI_MI2S_TX_2", LPI_MI2S_TX_2, \ + id, 1, 0, msm_routing_get_audio_mixer, \ + msm_routing_put_audio_mixer), \ + SOC_SINGLE_EXT("LPI_MI2S_TX_3", LPI_MI2S_TX_3, \ + id, 1, 0, msm_routing_get_audio_mixer, \ + msm_routing_put_audio_mixer), \ + SOC_SINGLE_EXT("LPI_MI2S_TX_4", LPI_MI2S_TX_4, \ + id, 1, 0, msm_routing_get_audio_mixer, \ + msm_routing_put_audio_mixer), \ + SOC_SINGLE_EXT("LPI_MI2S_TX_5", LPI_MI2S_TX_5, \ + id, 1, 0, msm_routing_get_audio_mixer, \ + msm_routing_put_audio_mixer), \ + SOC_SINGLE_EXT("LPI_MI2S_TX_6", LPI_MI2S_TX_6, \ id, 1, 0, msm_routing_get_audio_mixer, \ msm_routing_put_audio_mixer), @@ -711,6 +739,26 @@ static const struct snd_kcontrol_new rxcodec_dma_rx_6_mixer_controls[] = { static const struct snd_kcontrol_new rx_codec_dma_rx_7_mixer_controls[] = { Q6ROUTING_RX_MIXERS(RX_CODEC_DMA_RX_7) }; +static const struct snd_kcontrol_new lpi_mi2s_rx_0_mixer_controls[] = { + Q6ROUTING_RX_MIXERS(LPI_MI2S_RX_0) }; + +static const struct snd_kcontrol_new lpi_mi2s_rx_1_mixer_controls[] = { + Q6ROUTING_RX_MIXERS(LPI_MI2S_RX_1) }; + +static const struct snd_kcontrol_new lpi_mi2s_rx_2_mixer_controls[] = { + Q6ROUTING_RX_MIXERS(LPI_MI2S_RX_2) }; + +static const struct snd_kcontrol_new lpi_mi2s_rx_3_mixer_controls[] = { + Q6ROUTING_RX_MIXERS(LPI_MI2S_RX_3) }; + +static const struct snd_kcontrol_new lpi_mi2s_rx_4_mixer_controls[] = { + Q6ROUTING_RX_MIXERS(LPI_MI2S_RX_4) }; + +static const struct snd_kcontrol_new lpi_mi2s_rx_5_mixer_controls[] = { + Q6ROUTING_RX_MIXERS(LPI_MI2S_RX_5) }; + +static const struct snd_kcontrol_new lpi_mi2s_rx_6_mixer_controls[] = { + Q6ROUTING_RX_MIXERS(LPI_MI2S_RX_6) }; static const struct snd_kcontrol_new mmul1_mixer_controls[] = { Q6ROUTING_TX_MIXERS(MSM_FRONTEND_DAI_MULTIMEDIA1) }; @@ -940,6 +988,27 @@ static const struct snd_soc_dapm_widget msm_qdsp6_widgets[] = { SND_SOC_DAPM_MIXER("USB_RX Audio Mixer", SND_SOC_NOPM, 0, 0, usb_rx_mixer_controls, ARRAY_SIZE(usb_rx_mixer_controls)), + SND_SOC_DAPM_MIXER("LPI_MI2S_RX_0 Audio Mixer", SND_SOC_NOPM, 0, 0, + lpi_mi2s_rx_0_mixer_controls, + ARRAY_SIZE(lpi_mi2s_rx_0_mixer_controls)), + SND_SOC_DAPM_MIXER("LPI_MI2S_RX_1 Audio Mixer", SND_SOC_NOPM, 0, 0, + lpi_mi2s_rx_1_mixer_controls, + ARRAY_SIZE(lpi_mi2s_rx_1_mixer_controls)), + SND_SOC_DAPM_MIXER("LPI_MI2S_RX_2 Audio Mixer", SND_SOC_NOPM, 0, 0, + lpi_mi2s_rx_2_mixer_controls, + ARRAY_SIZE(lpi_mi2s_rx_2_mixer_controls)), + SND_SOC_DAPM_MIXER("LPI_MI2S_RX_3 Audio Mixer", SND_SOC_NOPM, 0, 0, + lpi_mi2s_rx_3_mixer_controls, + ARRAY_SIZE(lpi_mi2s_rx_3_mixer_controls)), + SND_SOC_DAPM_MIXER("LPI_MI2S_RX_4 Audio Mixer", SND_SOC_NOPM, 0, 0, + lpi_mi2s_rx_4_mixer_controls, + ARRAY_SIZE(lpi_mi2s_rx_4_mixer_controls)), + SND_SOC_DAPM_MIXER("LPI_MI2S_RX_5 Audio Mixer", SND_SOC_NOPM, 0, 0, + lpi_mi2s_rx_5_mixer_controls, + ARRAY_SIZE(lpi_mi2s_rx_5_mixer_controls)), + SND_SOC_DAPM_MIXER("LPI_MI2S_RX_6 Audio Mixer", SND_SOC_NOPM, 0, 0, + lpi_mi2s_rx_6_mixer_controls, + ARRAY_SIZE(lpi_mi2s_rx_6_mixer_controls)), SND_SOC_DAPM_MIXER("MultiMedia1 Mixer", SND_SOC_NOPM, 0, 0, mmul1_mixer_controls, ARRAY_SIZE(mmul1_mixer_controls)), SND_SOC_DAPM_MIXER("MultiMedia2 Mixer", SND_SOC_NOPM, 0, 0, @@ -1033,6 +1102,13 @@ static const struct snd_soc_dapm_route intercon[] = { Q6ROUTING_RX_DAPM_ROUTE("RX_CODEC_DMA_RX_6 Audio Mixer", "RX_CODEC_DMA_RX_6"), Q6ROUTING_RX_DAPM_ROUTE("RX_CODEC_DMA_RX_7 Audio Mixer", "RX_CODEC_DMA_RX_7"), Q6ROUTING_RX_DAPM_ROUTE("USB_RX Audio Mixer", "USB_RX"), + Q6ROUTING_RX_DAPM_ROUTE("LPI_MI2S_RX_0 Audio Mixer", "LPI_MI2S_RX_0"), + Q6ROUTING_RX_DAPM_ROUTE("LPI_MI2S_RX_1 Audio Mixer", "LPI_MI2S_RX_1"), + Q6ROUTING_RX_DAPM_ROUTE("LPI_MI2S_RX_2 Audio Mixer", "LPI_MI2S_RX_2"), + Q6ROUTING_RX_DAPM_ROUTE("LPI_MI2S_RX_3 Audio Mixer", "LPI_MI2S_RX_3"), + Q6ROUTING_RX_DAPM_ROUTE("LPI_MI2S_RX_4 Audio Mixer", "LPI_MI2S_RX_4"), + Q6ROUTING_RX_DAPM_ROUTE("LPI_MI2S_RX_5 Audio Mixer", "LPI_MI2S_RX_5"), + Q6ROUTING_RX_DAPM_ROUTE("LPI_MI2S_RX_6 Audio Mixer", "LPI_MI2S_RX_6"), Q6ROUTING_TX_DAPM_ROUTE("MultiMedia1 Mixer"), Q6ROUTING_TX_DAPM_ROUTE("MultiMedia2 Mixer"), Q6ROUTING_TX_DAPM_ROUTE("MultiMedia3 Mixer"), diff --git a/sound/soc/qcom/sc8280xp.c b/sound/soc/qcom/sc8280xp.c index b18996e412276..083515feabe93 100644 --- a/sound/soc/qcom/sc8280xp.c +++ b/sound/soc/qcom/sc8280xp.c @@ -37,6 +37,26 @@ static struct snd_soc_dapm_widget sc8280xp_dapm_widgets[] = { SND_SOC_DAPM_SPK("DP7 Jack", NULL), }; +static const struct snd_kcontrol_new max98090_controls[] = { + SOC_DAPM_PIN_SWITCH("Headset Mic12"), + SOC_DAPM_PIN_SWITCH("Headphone"), + SOC_DAPM_PIN_SWITCH("Headset Mic56"), + SOC_DAPM_PIN_SWITCH("Speaker"), + SOC_DAPM_PIN_SWITCH("Receiver"), + SOC_DAPM_PIN_SWITCH("Int Mic"), +}; + +static const struct snd_soc_dapm_widget max98090_dapm_widgets[] = { + SND_SOC_DAPM_HP("Headphone Jack", NULL), + SND_SOC_DAPM_MIC("Mic Jack", NULL), + SND_SOC_DAPM_HP("Headphone", NULL), + SND_SOC_DAPM_MIC("Headset Mic12", NULL), + SND_SOC_DAPM_MIC("Headset Mic56", NULL), + SND_SOC_DAPM_MIC("Int Mic", NULL), + SND_SOC_DAPM_SPK("Receiver", NULL), + SND_SOC_DAPM_SPK("Speaker", NULL), +}; + static struct snd_soc_dapm_widget shikra_cqm_dapm_widgets[] = { SND_SOC_DAPM_HP("Headphone Jack", NULL), SND_SOC_DAPM_MIC("Mic Jack", NULL), @@ -258,6 +278,7 @@ static int sc8280xp_snd_hw_params(struct snd_pcm_substream *substream, switch (cpu_dai->id) { case PRIMARY_MI2S_RX ... QUATERNARY_MI2S_TX: case QUINARY_MI2S_RX ... QUINARY_MI2S_TX: + case LPI_MI2S_RX_0 ... LPI_MI2S_TX_4: snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_BP_FP); if (pdata->snd_soc_common_priv->codec_dai_fmt) @@ -398,8 +419,12 @@ static struct snd_soc_common qcs6490_priv_data = { static struct snd_soc_common qcs8275_priv_data = { .driver_name = "qcs8300", - .dapm_widgets = sc8280xp_dapm_widgets, - .num_dapm_widgets = ARRAY_SIZE(sc8280xp_dapm_widgets), + .dapm_widgets = max98090_dapm_widgets, + .num_dapm_widgets = ARRAY_SIZE(max98090_dapm_widgets), + .controls = max98090_controls, + .num_controls = ARRAY_SIZE(max98090_controls), + .codec_sysclk_set = true, + .codec_dai_fmt = SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_BC_FC, }; static struct snd_soc_common sc8280xp_priv_data = {