Add f16 inline ASM support for 32-bit ARM

Author: beetrees

compiler/rustc_codegen_llvm/src/asm.rs

@@ -1020,6 +1020,19 @@ fn llvm_fixup_input<'ll, 'tcx>(
  value
 }
 }
+(
+InlineAsmRegClass::Arm(
+ArmInlineAsmRegClass::dreg
+ | ArmInlineAsmRegClass::dreg_low8
+ | ArmInlineAsmRegClass::dreg_low16
+ | ArmInlineAsmRegClass::qreg
+ | ArmInlineAsmRegClass::qreg_low4
+ | ArmInlineAsmRegClass::qreg_low8,
+),
+Abi::Vector{ element,count: count @ (4 | 8)},
+)if element.primitive() == Primitive::Float(Float::F16) => {
+ bx.bitcast(value, bx.type_vector(bx.type_i16(), count))
+}
 (InlineAsmRegClass::Mips(MipsInlineAsmRegClass::reg),Abi::Scalar(s)) => {
 match s.primitive(){
 // MIPS only supports register-length arithmetics.
@@ -1130,6 +1143,19 @@ fn llvm_fixup_output<'ll, 'tcx>(
  value
 }
 }
+(
+InlineAsmRegClass::Arm(
+ArmInlineAsmRegClass::dreg
+ | ArmInlineAsmRegClass::dreg_low8
+ | ArmInlineAsmRegClass::dreg_low16
+ | ArmInlineAsmRegClass::qreg
+ | ArmInlineAsmRegClass::qreg_low4
+ | ArmInlineAsmRegClass::qreg_low8,
+),
+Abi::Vector{ element,count: count @ (4 | 8)},
+)if element.primitive() == Primitive::Float(Float::F16) => {
+ bx.bitcast(value, bx.type_vector(bx.type_f16(), count))
+}
 (InlineAsmRegClass::Mips(MipsInlineAsmRegClass::reg),Abi::Scalar(s)) => {
 match s.primitive(){
 // MIPS only supports register-length arithmetics.
@@ -1233,6 +1259,19 @@ fn llvm_fixup_output_type<'ll, 'tcx>(
  layout.llvm_type(cx)
 }
 }
+(
+InlineAsmRegClass::Arm(
+ArmInlineAsmRegClass::dreg
+ | ArmInlineAsmRegClass::dreg_low8
+ | ArmInlineAsmRegClass::dreg_low16
+ | ArmInlineAsmRegClass::qreg
+ | ArmInlineAsmRegClass::qreg_low4
+ | ArmInlineAsmRegClass::qreg_low8,
+),
+Abi::Vector{ element,count: count @ (4 | 8)},
+)if element.primitive() == Primitive::Float(Float::F16) => {
+ cx.type_vector(cx.type_i16(), count)
+}
 (InlineAsmRegClass::Mips(MipsInlineAsmRegClass::reg),Abi::Scalar(s)) => {
 match s.primitive(){
 // MIPS only supports register-length arithmetics.

compiler/rustc_target/src/asm/arm.rs

@@ -47,16 +47,18 @@ impl ArmInlineAsmRegClass {
 _arch:InlineAsmArch,
 ) -> &'static[(InlineAsmType,Option<Symbol>)]{
 matchself{
-Self::reg => types!{ _:I8,I16,I32,F32;},
-Self::sreg | Self::sreg_low16 => types!{ vfp2:I32,F32;},
+Self::reg => types!{ _:I8,I16,I32,F16,F32;},
+Self::sreg | Self::sreg_low16 => types!{ vfp2:I32,F16,F32;},
 Self::dreg_low16 | Self::dreg_low8 => types!{
- vfp2:I64,F64,VecI8(8),VecI16(4),VecI32(2),VecI64(1),VecF32(2);
+ vfp2:I64,F64;
+ neon:VecI8(8),VecI16(4),VecI32(2),VecI64(1),VecF16(4),VecF32(2);
 },
 Self::dreg => types!{
- d32:I64,F64,VecI8(8),VecI16(4),VecI32(2),VecI64(1),VecF32(2);
+ d32:I64,F64;
+ neon:VecI8(8),VecI16(4),VecI32(2),VecI64(1),VecF16(4),VecF32(2);
 },
 Self::qreg | Self::qreg_low8 | Self::qreg_low4 => types!{
- neon:VecI8(16),VecI16(8),VecI32(4),VecI64(2),VecF32(4);
+ neon:VecI8(16),VecI16(8),VecI32(4),VecI64(2),VecF16(8),VecF32(4);
 },
 }
 }