Add targets: riscv32{e|em|emc}

- Based on riscv32{i|im|imc}
- Set data_layout stack alignment: S32 (bits)
- Set llvm_abiname = ilp32e

Author: hegza

compiler/rustc_target/src/spec/mod.rs

@@ -1841,6 +1841,10 @@ supported_targets! {
 ("riscv32imac-esp-espidf", riscv32imac_esp_espidf),
 ("riscv32imafc-esp-espidf", riscv32imafc_esp_espidf),
 
+("riscv32e-unknown-none-elf", riscv32e_unknown_none_elf),
+("riscv32em-unknown-none-elf", riscv32em_unknown_none_elf),
+("riscv32emc-unknown-none-elf", riscv32emc_unknown_none_elf),
+
 ("riscv32imac-unknown-none-elf", riscv32imac_unknown_none_elf),
 ("riscv32imafc-unknown-none-elf", riscv32imafc_unknown_none_elf),
 ("riscv32imac-unknown-xous-elf", riscv32imac_unknown_xous_elf),

compiler/rustc_target/src/spec/targets/riscv32e_unknown_none_elf.rs

@@ -0,0 +1,25 @@
+usecrate::spec::{Cc,LinkerFlavor,Lld,PanicStrategy,RelocModel,Target,TargetOptions};
+
+pubfntarget() -> Target{
+Target{
+data_layout:"e-m:e-p:32:32-i64:64-n32-S32".into(),
+llvm_target:"riscv32".into(),
+pointer_width:32,
+arch:"riscv32".into(),
+
+options:TargetOptions{
+linker_flavor:LinkerFlavor::Gnu(Cc::No,Lld::Yes),
+linker:Some("rust-lld".into()),
+cpu:"generic-rv32".into(),
+llvm_abiname:"ilp32e".into(),
+max_atomic_width:Some(32),
+atomic_cas:false,
+features:"+e,+forced-atomics".into(),
+panic_strategy:PanicStrategy::Abort,
+relocation_model:RelocModel::Static,
+emit_debug_gdb_scripts:false,
+eh_frame_header:false,
+ ..Default::default()
+},
+}
+}

compiler/rustc_target/src/spec/targets/riscv32em_unknown_none_elf.rs

@@ -0,0 +1,25 @@
+usecrate::spec::{Cc,LinkerFlavor,Lld,PanicStrategy,RelocModel,Target,TargetOptions};
+
+pubfntarget() -> Target{
+Target{
+data_layout:"e-m:e-p:32:32-i64:64-n32-S32".into(),
+llvm_target:"riscv32".into(),
+pointer_width:32,
+arch:"riscv32".into(),
+
+options:TargetOptions{
+linker_flavor:LinkerFlavor::Gnu(Cc::No,Lld::Yes),
+linker:Some("rust-lld".into()),
+cpu:"generic-rv32".into(),
+llvm_abiname:"ilp32e".into(),
+max_atomic_width:Some(32),
+atomic_cas:false,
+features:"+e,+m,+forced-atomics".into(),
+panic_strategy:PanicStrategy::Abort,
+relocation_model:RelocModel::Static,
+emit_debug_gdb_scripts:false,
+eh_frame_header:false,
+ ..Default::default()
+},
+}
+}

compiler/rustc_target/src/spec/targets/riscv32emc_unknown_none_elf.rs

@@ -0,0 +1,25 @@
+usecrate::spec::{Cc,LinkerFlavor,Lld,PanicStrategy,RelocModel,Target,TargetOptions};
+
+pubfntarget() -> Target{
+Target{
+data_layout:"e-m:e-p:32:32-i64:64-n32-S32".into(),
+llvm_target:"riscv32".into(),
+pointer_width:32,
+arch:"riscv32".into(),
+
+options:TargetOptions{
+linker_flavor:LinkerFlavor::Gnu(Cc::No,Lld::Yes),
+linker:Some("rust-lld".into()),
+cpu:"generic-rv32".into(),
+llvm_abiname:"ilp32e".into(),
+max_atomic_width:Some(32),
+atomic_cas:false,
+features:"+e,+m,+c,+forced-atomics".into(),
+panic_strategy:PanicStrategy::Abort,
+relocation_model:RelocModel::Static,
+emit_debug_gdb_scripts:false,
+eh_frame_header:false,
+ ..Default::default()
+},
+}
+}