🌐 Akdeniz University - Department of Computer Engineering

🖥️ CSE206 - Computer Organization

📌 Assignment #1: CPU Emulator

📝 Prepared by: Yahya Efe Kuruçay

🌐 Website: efekurucay.com

📅 Last Update: 11/05/2025

Student ID	20220808005

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🚀 Project Description

⚡ Submission Note

This assignment reflects a comprehensive development effort. Collaboration with my roommate, Burak Yalçın (Student ID: 20220808069), was crucial. Our discussions refined our understanding of:

• Addressing Modes
• Program Counter (PC) Increment Logic
• Cache Interaction

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📂 Project Structure

File	Description
Memory.java	Simulates 64 KB main memory with byte-level read/write operations.
Cache.java	Implements a direct-mapped cache with 16 bytes (8 blocks, 2 bytes each).
CPUEmulator.java	Manages CPU logic, including fetch-decode-execute cycle.
Main.java	Application entry point; loads and executes the program.

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📝 System Specifications & Implementation Details

🔧 CPU Registers

Register	Description
Program Counter (PC)	Stores the next instruction address.
Accumulator (AC)	16-bit register for arithmetic/logical operations.
Comparison Flag	Set to -1, 0, or 1 by comparison instructions.

📊 Main Memory

Specification	Details
Capacity	65,536 bytes (64 KB)
Addressability	Byte-addressable
Endianness	Little-endian (16-bit values)

🔠 Instruction Format

Property	Details
Size	16-bit
Structure	4-bit opcode + 12-bit operand
Storage	Each instruction occupies 2 bytes

🚀 Program Loading

• Loaded into main memory starting at the loadAddress from config.txt.
• Each 16-bit instruction occupies 2 consecutive bytes.

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🔎 Addressing Modes

Mode	Description
Immediate	Operand contains the direct value (for LOAD, ADD, SUB, MUL).
Relative	Effective address is loadAddress + operand.
Absolute	(For PC/Jumps) loadAddress + operand * 2.

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📈 Cache Implementation Details

Property	Value
Cache Size	16 bytes
Block Size	2 bytes
Number of Blocks	8 (16 bytes / 2 bytes/block)
Mapping	Direct-Mapped

✅ Policies

Policy	Description
Write-Through	Writes immediately update main memory.
Write-Allocate	On write miss, block fetched from memory before writing.

📐 Address Breakdown

Field	Size	Purpose
Offset	1 bit	Selects the byte within a 2-byte block.
Index	3 bits	Selects one of 8 cache blocks.
Tag	12 bits	Verifies cache hit.

⚡ Cache Accesses

• All data memory operations (LOADM, STOREM, etc.) pass through the cache.
• Instruction fetches also utilize the cache, contributing to access stats.

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🚧 Development Challenges & Resolution

⚡ Addressing Mode Ambiguity

Issue	Solution
Interpreting "Absolute (for PC/Jumps)"	Treated jump operands as relative instruction indices.

🔄 PC Increment and Fetch Logic

Standard Behavior	Adjusted Behavior
PC += 2 after each instruction	Fetches counted as cache accesses for hit/miss stats.

✅ Final Implementation Approach

1. Program Loading: Directly into the Memory object.
2. Instruction Fetching: Via cache, affecting hit/miss ratio.
3. PC Management: Increments by 2, except for jumps.
4. Jump Calculation:loadAddress + operand * 2.
5. Memory Operations: Accessed through cache.

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🔧 Debugging and Notes

• Extensive use of System.out.println for tracing execution.
• Memory operand instructions (LOADM, STOREM, etc.) operate on single bytes.
• Little-endian byte ordering for 16-bit instructions.
• Named constants (e.g., VALID, TAG in Cache.java) for clarity.

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📌 Sample Program Execution and Output

Configuration	Value
Program Load Address	0x2000
Initial PC	0x2000
Final AC Value	210
Cache Hit Ratio	72.88%

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📦 Submission Files

File	Description
README.md	This file (documentation).
CPUEmulator.java	Core CPU emulation logic.
Cache.java	Direct-mapped cache implementation.
Memory.java	Main memory simulation (64 KB).
Main.java	Application entry point.
program.txt	Original sample program.
config.txt	Configuration file.
program2.txt	Custom factorial test program (for verification).

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