ChipFlow Training

Training materials for learning the ChipFlow platform — a cloud-based RTL-to-GDS chip design service.

What's included

• Creating a Design for Use with the ChipFlow Platform — how to create a new design from scratch for the ChipFlow platform
• Hard-Macro Builds (package = "block") — produce a LEF + Liberty + GDS + blackbox stub for a parent chip, instead of a packaged chip
• Using Hard Macros (load_blackbox_wrapper) — instantiate NDA / third-party hard macros (or your own block builds) inside an Amaranth design
• Wrapping External RTL — integrating existing Verilog or SystemVerilog modules into an Amaranth design (manual Instance)
• RTLWrapper (TOML-based wrapping) — higher-level wrapper with auto-mapping and sv2v preprocessing
• Wrapping CV32E40P — worked example: wrapping the OpenHW Group RISC-V core with sv2v and RTLWrapper
• Upcounter example — a simple Amaranth HDL design targeting the IHP SG13G2 130nm process, ready to build and submit to the platform
• Training Command Reference — step-by-step guide covering prerequisites, setup, authentication, building, and submitting designs
• chipflow.toml Reference — complete configuration format documentation
• Simulation — testing designs locally with CXXRTL-based simulation
• Upcounter Simulation Walkthrough — step-by-step guide to simulating the upcounter with waveforms

Quick start

# Clone this repo
git clone https://github.com/ChipFlow/chipflow-training.git
cd chipflow-training
# Install dependencies
make init
# Build and submit the upcounter design
make upcounter-submit

See the Training Command Reference for detailed instructions including prerequisites for macOS, Linux, and Windows.

Project structure

chipflow-training/
├── Makefile # Build commands
├── pyproject.toml # Python dependencies
├── getting-started-design.md # How to write a new design
├── block-package.md # Hard-macro / IP block builds
├── using-hard-macros.md # Instantiating hard macros via load_blackbox_wrapper
├── wrapping-external-rtl.md # Wrapping Verilog / SystemVerilog IP (manual Instance)
├── rtl-wrapper.md # TOML-based RTLWrapper reference
├── cv32e40p-example.md # CV32E40P worked example
├── training-commands.md # Full training guide
├── chipflow-toml-reference.md # Configuration reference
├── simulation.md # Simulation guide
└── upcounter/
├── chipflow.toml # Design config (process, package)
└── design/
└── design.py # Amaranth HDL upcounter design

Links

• ChipFlow Platform
• chipflow-lib — core client library
• chipflow-examples — additional example designs