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DerathThutaram/README.md

Hey, It's Derath

ECE Student @ VIT Vellore | Aspiring VLSI Design Verification Engineer

  • 🔭 Focus Areas: Digital Design, SystemVerilog, UVM, Protocol Verification (AMBA AHB/APB), RISC-V Verification
  • 🛠️ Skills & Tools: SystemVerilog, Verilog, C++, Python, ModelSim, Git
  • 📫 LinkedIn: https://www.linkedin.com/in/derath-thutaram

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  1. ahb-apb-bridge-verification ahb-apb-bridge-verification Public

    SystemVerilog testbench for verifying AMBA AHB-to-APB bus protocol bridge

    SystemVerilog

  2. riscv-hazard-verification riscv-hazard-verification Public

    RTL design and verification of hazard detection and forwarding logic for a 5-stage RISC-V pipeline.

    SystemVerilog