An Open-Source EDA Tool for Circuit Design, Simulation, Analysis & PCB Design
Developed by FOSSEE Team at IIT Bombay
Features • Architecture • Installation • Project Structure • Tech Stack • Contributing • License
eSim is a free and open-source EDA (Electronic Design Automation) tool for circuit design, simulation, analysis, and PCB design. It is an integrated tool built using open-source software such as KiCad, Ngspice, GHDL, and Makerchip, providing a seamless workflow from schematic capture to simulation results.
eSim is designed for electronics engineers, students, educators, and hobbyists who want a powerful yet cost-free alternative to proprietary EDA tools. It supports analog, digital, and mixed-signal simulations, including microcontroller integration.
📥 Download:v2.5 Release | 📄 Manual:PDF Guide | 📚 Docs:ReadTheDocs
| Category | Feature | Description |
|---|---|---|
| • Design | Schematic Capture | Draw circuit schematics using KiCad's schematic editor with eSim's custom symbol libraries |
| • Conversion | KiCad to Ngspice | Convert KiCad schematics to Ngspice-compatible netlists for simulation |
| • Simulation | Ngspice Engine | Run DC, AC, Transient, and other SPICE analyses with real-time interactive plots |
| • Analysis | Waveform Plotting | Visualize simulation results with matplotlib-based Python plots and Ngspice native plots |
| • Model Editor | Device Models | Create and edit SPICE device models (Diodes, BJTs, MOSFETs, JFETs, IGBTs, etc.) |
| • Subcircuits | Subcircuit Builder | Build, manage, and upload reusable subcircuit blocks — 741+ ICs in SubcircuitLibrary |
| • Mixed-Signal | NGHDL Integration | Interface VHDL digital models (via GHDL) with analog Ngspice simulations |
| • Verilog | Makerchip + NgVeri | Use Makerchip IDE for Verilog/TL-Verilog design and convert to Ngspice models |
| • PCB | Layout Design | Design PCB layouts using KiCad's PCB editor with eSim's footprint libraries |
| • Converters | Schematic Import | Convert PSpice and LTSpice schematics/libraries to KiCad-compatible formats |
| • Modelica | Ngspice-to-Modelica | Convert Ngspice netlists to Modelica models for OpenModelica simulation |
| • SKY130 PDK | SkyWater 130nm | Support for SkyWater SKY130 open-source Process Design Kit |
| • IHP PDK | IHP OpenPDK | Integration with IHP SG13G2 open-source PDK for SiGe BiCMOS |
graph TB
%% Styling
classDef ui fill:#2A3F54,stroke:#1ABB9C,stroke-width:2px,color:#fff
classDef core fill:#3E536C,stroke:#3498DB,stroke-width:2px,color:#fff
classDef engine fill:#1F2D3D,stroke:#E74C3C,stroke-width:2px,color:#fff
classDef data fill:#E9F0F5,stroke:#95A5A6,stroke-width:1px,color:#333
subgraph UI ["User Interface (PyQt6)"]
A[Application Main Window]:::ui
PE[Project Explorer]:::ui
DA[Dock Area Workspace]:::ui
TE[Time Explorer]:::ui
CON[Console Widget]:::ui
A --> PE & DA & TE & CON
end
subgraph CORE ["Core Python Modules"]
K2N[KiCad-to-Ngspice]:::core
SIM[Ngspice Simulator]:::core
PLT[Matplotlib Plotter]:::core
ME[Model Editor]:::core
SC[Subcircuit Builder]:::core
DA --> K2N & SIM & ME & SC
end
subgraph INTEGRATION ["Mixed-Signal & External APIs"]
NGHDL[NGHDL Interface]:::core
MKR[Makerchip/NgVeri]:::core
MOD[Modelica Converter]:::core
CONV[PSpice/LTSpice Converter]:::core
DA --> NGHDL & MKR & MOD & CONV
end
subgraph ENGINES ["Simulation & EDA Engines"]
KICAD[KiCad Eeschema]:::engine
PCB[KiCad Pcbnew]:::engine
NGSPICE[Ngspice Backend]:::engine
GHDL[GHDL Simulator]:::engine
VER[Verilator]:::engine
OM[OpenModelica]:::engine
end
%% Data Flow
XML[(Netlist / XML)]:::data
RAW[(Raw Data / txt)]:::data
VHDL[(VHDL Files)]:::data
K2N -- Generates --> XML
XML -- Consumed by --> NGSPICE
SIM -- Triggers --> NGSPICE
NGSPICE -- Outputs --> RAW
RAW -- Parsed by --> PLT
NGHDL -- Compiles --> VHDL
VHDL -- Simulated by --> GHDL
GHDL -- Co-simulates --> NGSPICE
MKR -- Verilog/TL-V --> VER
KICAD -- Schematic --> K2N
KICAD -- Netlist --> PCB
For detailed simulation workflows, sub-system operations, and system flowcharts, please refer to our Architecture & Workflows Guide.
| Path | Type | Description |
|---|---|---|
src/ | 📁 Directory | Core application source code — all Python modules for the eSim GUI and backend |
library/ | 📁 Directory | Component libraries — device models, KiCad symbols, subcircuits, and PDK data |
nghdl/ | 📁 Directory | NGHDL module — Ngspice-GHDL interface for mixed-signal VHDL simulation |
Examples/ | 📁 Directory | 42 example projects — ready-to-simulate circuits (RC, BJT, Op-Amp, Mixed-Signal, etc.) |
images/ | 📁 Directory | UI assets — application icons, toolbar images, logos, and splash screen |
scripts/ | 📁 Directory | Launch & setup scripts — shell scripts for Linux installation and launching |
docs/ | 📁 Directory | Sphinx documentation — RST files for ReadTheDocs auto-generated developer docs |
code/ | 📁 Directory | Sphinx autodoc config — mirrors src/ structure for API documentation generation |
flatpak/ | 📁 Directory | Flatpak packaging — manifest and wrapper scripts for universal Linux distribution |
appimage/ | 📁 Directory | AppImage packaging — build scripts for portable Linux AppImage bundles |
docker-launcher/ | 📁 Directory | Docker support — Dockerfile, launcher script, and CI workflows for containerized builds |
snap/ | 📁 Directory | Snap packaging — snapcraft.yaml for building Snap packages |
ihp/ | 📁 Directory | IHP PDK integration — install script, .spiceinit config, NMOS example, and ngspice latest installer for IHP SG13G2 SiGe BiCMOS PDK |
patches/ | 📁 Directory | Source patches — patch files for modifying Ngspice/GHDL behavior in sandboxed environments |
.github/ | 📁 Directory | GitHub config — issue templates, PR templates, and CI/CD workflow definitions |
setup.py | 📄 File | Python package configuration for pip installation |
requirements.txt | 📄 File | Python dependency list (PyQt6, matplotlib, numpy, scipy, etc.) |
conf.py | 📄 File | Sphinx documentation configuration |
VERSION | 📄 File | Current version identifier (2.5) |
INSTALL | 📄 File | Detailed multi-platform installation instructions |
LICENSE | 📄 File | GNU General Public License v3.0 |
src/
├── frontEnd/ # GUI & Main Application
│ ├── Application.py # Main window, toolbar setup, menu actions (960 lines)
│ ├── DockArea.py # Tabbed dock workspace for editors/simulators (24K)
│ ├── ProjectExplorer.py # File tree browser for project navigation (20K)
│ ├── TimeExplorer.py # Project snapshot/version management (8K)
│ ├── TerminalUi.py # Embedded terminal widget (5K)
│ └── Workspace.py # Workspace selection dialog (6K)
│
├── kicadtoNgspice/ # KiCad-to-Ngspice Conversion Engine
│ ├── KicadtoNgspice.py # Main conversion controller & UI (41K)
│ ├── Convert.py # Netlist parsing and SPICE generation (40K)
│ ├── Analysis.py # Analysis type configuration (DC, AC, Transient) (32K)
│ ├── DeviceModel.py # Device model parameter handling (56K)
│ ├── Source.py # Source component configuration (15K)
│ ├── Processing.py # Netlist processing pipeline (26K)
│ ├── SubcircuitTab.py # Subcircuit selection in converter (9K)
│ ├── Microcontroller.py # Microcontroller model support (10K)
│ ├── Model.py # Model file handling (6K)
│ └── TrackWidget.py # UI tracking widget (1K)
│
├── ngspiceSimulation/ # Simulation Engine & Plotting
│ ├── NgspiceWidget.py # Ngspice process management & execution (16K)
│ ├── plot_window.py # matplotlib-based waveform plotter (66K)
│ ├── plotting_widgets.py # Custom plot controls and widgets (8K)
│ └── data_extraction.py # Simulation data file parser (11K)
│
├── modelEditor/ # SPICE Model Editor
│ └── ModelEditor.py # GUI for creating/editing device models (33K)
│
├── subcircuit/ # Subcircuit Management
│ ├── Subcircuit.py # Subcircuit manager main window (3K)
│ ├── newSub.py # Create new subcircuit (3K)
│ ├── openSub.py # Open existing subcircuit (1K)
│ ├── uploadSub.py # Upload subcircuit to library (4K)
│ └── convertSub.py # Subcircuit format conversion (2K)
│
├── maker/ # Makerchip & NgVeri Integration
│ ├── Maker.py # Makerchip IDE integration (23K)
│ ├── NgVeri.py # Verilog-to-Ngspice model generator (17K)
│ ├── ModelGeneration.py # Auto model generation pipeline (48K)
│ ├── createkicad.py # KiCad symbol creation for models (14K)
│ ├── makerchip.py # Makerchip cloud IDE connector (3K)
│ └── Appconfig.py # Maker-specific configuration (2K)
│
├── converter/ # Schematic Format Converters
│ ├── pspiceToKicad.py # PSpice schematic importer (5K)
│ ├── ltspiceToKicad.py # LTSpice schematic importer (6K)
│ ├── libConverter.py # Library format converter (3K)
│ ├── LtspiceLibConverter.py # LTSpice library converter (4K)
│ ├── browseSchematic.py # File browser for schematics (550B)
│ ├── LTSpiceToKiCadConverter/ # LTSpice conversion engine
│ └── schematic_converters/ # Additional schematic parsers
│
├── ngspicetoModelica/ # 📐 Ngspice-to-Modelica Converter
│ ├── NgspicetoModelica.py # Core conversion engine (54K)
│ └── ModelicaUI.py # Modelica converter GUI (10K)
│
├── configuration/ # ⚙️ Application Configuration
│ └── Appconfig.py # Global config, paths, process tracking (4K)
│
├── projManagement/ # 📋 Project Management
│ ├── Kicad.py # KiCad integration (launch schematic/PCB editor) (9K)
│ ├── Validation.py # Tool and file validation utilities (7K)
│ ├── Worker.py # Background process/thread management (3K)
│ ├── newProject.py # New project creation logic (5K)
│ └── openProject.py # Open existing project logic (3K)
│
└── browser/ # 📖 Help & Documentation
├── Welcome.py # Welcome screen display (941B)
└── UserManual.py # User manual viewer (731B)
| Path | Description |
|---|---|
deviceModelLibrary/ | SPICE device models organized by type: Diode, BJT (Transistor), MOSFET (MOS), JFET, IGBT, LEDs, Switches, Transmission Lines, and user libraries |
kicadLibrary/ | KiCad schematic symbols (eSim-symbols/), footprint libraries (kicad_eSim-Library/), and project templates |
SubcircuitLibrary/ | 741+ reusable subcircuit ICs — logic gates, flip-flops, op-amps, regulators, timers, multiplexers, shift registers, comparators, multipliers, PDK-specific IPs, and more (see Subcircuit Library section) |
modelParamXML/ | XML parameter definitions for device model editor forms |
ngspicetoModelica/ | Mapping files for Ngspice-to-Modelica component translation |
browser/ | HTML/resource files for the built-in help browser |
tlv/ | TL-Verilog support files for Makerchip integration |
| Path | Description |
|---|---|
src/ngspice_ghdl.py | Core interface: manages VHDL upload, GHDL compilation, and Ngspice code model creation |
src/model_generation.py | Generates C code models from VHDL port definitions for Ngspice |
src/createKicadLibrary.py | Auto-generates KiCad symbols from VHDL entity definitions |
src/ghdlserver/ | GHDL foreign interface server for inter-process communication with Ngspice |
install-nghdl.sh | Automated installer for NGHDL dependencies (GHDL, Verilator, Ngspice) |
Example/ | Example VHDL models and mixed-signal simulation projects (including Microwatt NGHDL co-simulation) |
| Path | Description |
|---|---|
ihp-install-script.sh | Automated installer for IHP SG13G2 open-source SiGe BiCMOS PDK |
install-ngspice-latest.sh | Script to build and install the latest ngspice from source (with OSDI support) — requires eSim/NGHDL to be installed first |
.spiceinit | Pre-configured .spiceinit file for IHP-Open-PDK; automatically placed in the home directory after configuration |
example.cir | NMOS DC test circuit demonstrating IHP PDK SPICE simulation |
| Layer | Technology | Purpose |
|---|---|---|
| Language |  | Core application logic |
| GUI Framework |  | Desktop GUI (windows, dialogs, toolbars, docks) |
| Plotting |  | Waveform visualization and data plotting |
| Numerics |   | Numerical computation and signal processing |
| Schematic & PCB |  | Schematic capture and PCB layout design |
| SPICE Simulation |  | Analog/mixed-signal circuit simulation engine |
| VHDL Simulation |  | VHDL analysis, compilation, and simulation |
| Verilog |  | Verilog HDL simulation and model generation |
| HDL Cloud IDE |  | Online Verilog/TL-Verilog IDE integration |
| Modelica |  | Multi-domain modeling and simulation |
| PDK |   | SkyWater 130nm & IHP SiGe BiCMOS open-source PDKs |
| Packaging |   | Cross-distribution Linux packaging & containers |
| Documentation |   | Auto-generated developer documentation |
| CI/CD |  | Automated builds, Docker images, and releases |
| Package | Version | Purpose |
|---|---|---|
PyQt6 | ≥ 6.5.0 | GUI framework |
matplotlib | 3.7.5 | Waveform plotting |
numpy | 1.24.4 | Numerical computation |
scipy | 1.10.1 | Scientific computing |
pillow | 12.2.0 | Image processing |
hdlparse | 1.0.4 | HDL file parsing |
watchdog | 4.0.2 | File system monitoring |
pyparsing | 3.1.4 | Parser building toolkit |
| Platform | Method | Status |
|---|---|---|
| All Linux (Fedora, Ubuntu, openSUSE, Arch, etc.) | Flatpak | ✅ Recommended |
| Ubuntu 22.04 / 23.04 / 24.04 LTS | Native Installer | ✅ Supported |
| Windows 8 / 10 / 11 | Windows Installer | ✅ Supported |
| Docker (any OS) | Docker Container | ✅ Supported |
# 1. Install Flatpak (if not already installed)# Fedora: sudo dnf install flatpak# Ubuntu: sudo apt install flatpak# openSUSE: sudo zypper install flatpak# Arch: sudo pacman -S flatpak# 2. Add Flathub repository
flatpak remote-add --if-not-exists flathub https://dl.flathub.org/repo/flathub.flatpakrepo
# 3. Install eSim
flatpak install flathub org.fossee.eSim
# 4. Run eSim
flatpak run org.fossee.eSim
⚠️ Flatpak Limitations: NGHDL, Makerchip, and SKY130 PDK are not included in the Flatpak build. For full mixed-signal support, use the Ubuntu native installer.
# 1. Download and extract eSim
unzip eSim-2.5.zip
cd eSim-2.5
# 2. Install eSim with all dependencies
chmod +x install-eSim.sh
./install-eSim.sh --install
# 3. Run eSim
esim
# Or double-click the eSim desktop icon- Download the eSim installer from esim.fossee.in/downloads
- Disable antivirus temporarily (if required)
- Important: Remove MinGW/MSYS from the PATH environment variable if previously installed
- Run the installer and follow the on-screen instructions
- Launch eSim from the Start Menu or desktop shortcut
Refer to the Docker Launcher README for instructions on running eSim in a containerized environment.
Note: The Docker image now includes
libreadline-devto fix a build issue on recent Ubuntu base images.
cd eSim
flatpak-builder build flatpak/org.fossee.eSim.yml --install --user📖 For comprehensive installation instructions, see the INSTALL file.
If you need the latest Ngspice with OSDI support for IHP PDK simulations:
# Requires eSim/NGHDL to be installed first
chmod +x ihp/install-ngspice-latest.sh
./ihp/install-ngspice-latest.sh| Workflow | File | Purpose |
|---|---|---|
| Docker Image Build | .github/workflows/docker-image.yml | Builds and publishes the eSim Docker image |
| Docker Launcher Build | .github/workflows/docker-launcher-build.yml | Builds the cross-platform Python launcher |
| Ubuntu Release | .github/workflows/release_ubuntu.yml | Automated Ubuntu .deb package builds |
| Packaging Format | Directory | Description |
|---|---|---|
| Flatpak | flatpak/ | Universal Linux package via Flathub |
| AppImage | appimage/ | Portable single-file Linux executable |
| Snap | snap/ | Ubuntu Snap Store package |
| Docker | docker-launcher/ | Containerized distribution with GUI forwarding |
eSim ships with 42 ready-to-simulate example projects in the Examples/ directory:
📂 Click to expand full example list
| # | Category | Example | Description |
|---|---|---|---|
| 1 | 🔌 Basic | RC | RC circuit transient analysis |
| 2 | 🔌 Basic | RL | RL circuit transient analysis |
| 3 | 🔌 Basic | RLC | RLC circuit resonance analysis |
| 4 | 🔌 Basic | Series_Resonance | Series RLC resonance |
| 5 | 🔌 Basic | Parallel_Resonance | Parallel RLC resonance |
| 6 | 💡 Diodes | Diode_characteristics | Diode I-V characteristics |
| 7 | 💡 Diodes | Halfwave_Rectifier | Half-wave rectifier circuit |
| 8 | 💡 Diodes | Fullwavebridgerectifier | Full-wave bridge rectifier |
| 9 | 💡 Diodes | Clippercircuit | Diode clipper circuit |
| 10 | 💡 Diodes | Clampercircuit | Diode clamper circuit |
| 11 | 💡 Diodes | Zener_Characteristic | Zener diode characteristics |
| 12 | 🔋 BJT | BJT_CE_config | BJT common-emitter configuration |
| 13 | 🔋 BJT | BJT_CB_config | BJT common-base configuration |
| 14 | 🔋 BJT | BJT_amplifier | BJT amplifier circuit |
| 15 | 🔋 BJT | BJT_Biascircuit | BJT bias circuit design |
| 16 | 🔋 BJT | BJT_Frequency_Response | BJT frequency response analysis |
| 17 | 📟 FET | FET_Characteristic | FET output characteristics |
| 18 | 📟 FET | FET_Amplifier | FET amplifier circuit |
| 19 | 📟 FET | FrequencyResponse_JFET | JFET frequency response |
| 20 | 🎛️ Op-Amp | InvertingAmplifier | Op-amp inverting amplifier (LM741) |
| 21 | 🎛️ Op-Amp | Differentiator | Op-amp differentiator circuit |
| 22 | 🎛️ Op-Amp | Integrator_LM_741 | Op-amp integrator |
| 23 | 🎛️ Op-Amp | Precision_Rectifiers_using_LM741 | Precision rectifier circuits |
| 24 | 🔲 Digital | BasicGates | Basic logic gates |
| 25 | 🔲 Digital | Half_Adder | Half-adder circuit |
| 26 | 🔲 Digital | FullAdder | Full-adder circuit |
| 27 | 🔲 Digital | JK_Flipflop | JK flip-flop circuit |
| 28 | 🔲 Digital | 4_bit_JK_ff | 4-bit JK flip-flop counter |
| 29 | 🔲 Digital | CMOS_NAND_Gate | CMOS NAND gate |
| 30 | 🔲 Digital | Analysis_Of_Digital_IC | Digital IC analysis |
| 31 | ⏱️ Timers | Astable555 | 555 timer astable mode |
| 32 | ⏱️ Timers | Monostable555 | 555 timer monostable mode |
| 33 | 🔁 SCR | HalfwaveRectifier_SCR | SCR half-wave rectifier |
| 34 | 🔁 SCR | FullwaveRectifier_SCR | SCR full-wave rectifier |
| 35 | 📡 Filters | High_Pass_Filter | High-pass filter design |
| 36 | 📡 Filters | Low_Pass_Filter | Low-pass filter design |
| 37 | ⚡ Regulators | 7805VoltageRegulator | 7805 voltage regulator |
| 38 | ⚡ Regulators | 7812VoltageRegulator | 7812 voltage regulator |
| 39 | 🌀 Oscillators | UJT_Relaxation_Oscillator | UJT relaxation oscillator |
| 40 | 🌀 Oscillators | Phase_Locked_Loop | PLL circuit |
| 41 | 🔀 Mixed-Signal | Mixed_Signal | Mixed analog-digital simulation (NGHDL) |
| 42 | 🔌 Power | Transformer | Transformer circuit analysis |
The library/SubcircuitLibrary/ directory contains 741+ verified subcircuit models contributed by the community. These can be directly used in eSim simulations as subcircuit blocks.
📂 Click to expand subcircuit categories
| Category | Examples |
|---|---|
| Logic Gates & Buffers | 74HC08, 74HC32, 74HC86, SN74LS00, IC74HC00, INVCMOS, CMOS_NAND, SNx4HC03 |
| Flip-Flops & Latches | 74LS379, CD4095BMS, JK flip-flops (74LS112, IC74HC107), D flip-flops, SR latches |
| Shift Registers | 74hc589, 74HCT594, 74LS298, 74LS399, SN74LS295B, SN74LS194 |
| Multiplexers / Demultiplexers | 74LS150 (16:1 MUX), 74HC157, CD4051_sub, SN74LS451, 74ls670 |
| Counters & Dividers | CD4017B, CD4026B, CD4029B, 74ls93, 74ls181, SN74LS461, DM74ls173 |
| Encoders / Decoders | SN74LS247, SN74LS353, MM74C923, CD4099B, CD4089B, LM3914 |
| Op-Amps & Comparators | LM358_Sub, LM741, LM311, LM393, LT1010, lmh6702, opa656, ths4303, ths4541 |
| Voltage Regulators | LM7806, LM7812, LP2950, LP2951, LM317_sub, MCP1700, TCA965, MC1569_Sub |
| Audio Amplifiers | MC1306_Sub, MC1554_Sub, LM386, LM833, TDA2003A_sub |
| RF / IF Amplifiers | MC1510_sub, MC1545_Sub, MC1550_Sub, vca821 |
| Multipliers & Modulators | ad834, ad8307, MC1595_Sub, MC1596_Sub, cppll |
| Motor Drivers & Power ICs | L298N, IR2110, IR2130, IP5328P, TP4056, MCP73831, TL494 |
| CA-Series ICs | CA3005, CA3018, CA3019, CA3022, CA3028A, CA3036, CA3054, CA3080, CA3094 |
| SN74-Series ICs | SN74AS303, SN74AS304, SN74AS305, SN74LS247, SN74LS451, SN74S268, SN74S532, SN74S536, SN74278 |
| MC-Series ICs | MC1306_Sub, MC1510_sub, MC1545_Sub, MC1550_Sub, MC1554_Sub, MC1569_Sub, MC1595_Sub, MC1596_Sub |
| CD/CMOS Series | CD4016, CD4026B, CD4029B, CD4089B, CD4095BMS, CD4099B, CD74HC563, CD74HCT241 |
| ADC / DAC | 3bit_flash_adc, DAC0800, 10bitDAC |
| Timers | NE556 (dual 555), lm555n, MC1455B_IC |
| Miscellaneous | SN54170, LM2902, LM2904, LM2917, LM2941, TL783, _TL783 |
💡 Contributing a Subcircuit? Follow the guidelines in CONTRIBUTING.md. Each subcircuit should include a
.subSPICE file, a KiCad schematic (.kicad_sch), and a test circuit (.cir).
We welcome contributions from the community! Whether it's bug fixes, new features, documentation improvements, or example circuits — every contribution matters.
flowchart LR
A["🍴 Fork<br/>Repository"] --> B["🌿 Create<br/>Branch"]
B --> C["💻 Make<br/>Changes"]
C --> D["✅ Commit &<br/>Push"]
D --> E["📬 Open<br/>Pull Request"]
style A fill:#6c5ce7,color:#fff
style B fill:#00b894,color:#fff
style C fill:#0984e3,color:#fff
style D fill:#fdcb6e,color:#333
style E fill:#e17055,color:#fff
- Fork the repository to your GitHub account
- Clone your fork:
git clone https://github.com/<your-username>/eSim.git
- Create a new branch for your changes:
git checkout -b feature/your-feature-name
- Make your changes and commit with a descriptive message:
git add <files> git commit -m "Fixes issue #<number> - Brief description of changes"
- Push to your fork and open a Pull Request:
git push origin feature/your-feature-name
📌 Guidelines:
- Each PR should reference an existing issue
- One commit per pull request (squash if needed)
- Follow PEP 8 code style
- Include a commit body describing what you changed and why
For detailed contribution guidelines, see CONTRIBUTING.md.
A huge thank you to all 149+ amazing people who have contributed to eSim! 🎉
 🥇 Sumanto Kar Lead Maintainer · 320 commits |  🥈 Rahul Paknikar 265 commits |  🥉 Fahim Khan 244 commits |
149+ contributors and counting! View all contributors →
| Channel | Link |
|---|---|
| contact-esim@fossee.in | |
| 🌐 Website | esim.fossee.in |
| 💬 Forum | forums.fossee.in |
| 📞 Contact Page | esim.fossee.in/contact-us |
| 📄 User Manual | eSim Manual v2.5 (PDF) |
| 📚 Developer Docs | esim.readthedocs.io |
A summary of notable changes since the last README update (June 2026):
- Added
ihp/install-ngspice-latest.sh— a script to build the latest Ngspice from source with OSDI support for IHP PDK users - Added
ihp/.spiceinit— pre-configured Ngspice initialization file for IHP-Open-PDK; the install script now correctly places it in the user's home directory - Added
ihp/example.cir— an NMOS DC test circuit demonstrating IHP PDK simulation
Over 100 new subcircuit ICs were contributed and verified, bringing the total to 741+ entries in library/SubcircuitLibrary/. Highlights include:
- CA-series ICs: CA3005, CA3018, CA3019, CA3022, CA3028A, CA3036, CA3054 (and moved CA3020, CA3021, etc. from misplaced locations)
- MC-series analog ICs: MC1306_Sub (audio amp), MC1510_sub (RF/IF amp), MC1545_Sub (video amp), MC1550_Sub (RF/IF amp), MC1554_Sub (audio amp), MC1569_Sub (voltage regulator), MC1595_Sub (4-quadrant multiplier), MC1596_Sub (balanced modulator/demodulator)
- Analog ICs from PR #604 (Farhana): LT1010, vca821, ths4541, ths4303, opa656, lmh6702, cppll, ad834, ad8307, 3bit_flash_adc
- Power/control ICs: L298N (motor driver), IR2110, IR2130 (gate drivers), IP5328P (power bank IC), TP4056 (Li-ion charger), MCP73831 (Li-Po charger), TL494 (PWM controller), TL783, LP2950, LP2951
- Voltage regulators: LM2941, LM7806, MCP1700, TCA965
- Op-amps / comparators: LM2902, LM2904, LM2917, LM1815
- SN74-series digital ICs: SN74AS303/304/305, SN74LS247, SN74LS295B, SN74LS353, SN74LS451, SN74LS461, SN74LS498, SN74S268, SN74S532, SN74S536, SN74278
- TTL/CMOS logic: 74LS112, 74LS150, 74LS298, 74LS379, 74LS399, 74hc589, 74HCT594, CD4095BMS, CD4016, CD4026B, CD4029B, CD4089B, CD4099B, SN54170, MM74C923, LM3914
- Additional digital ICs: 74ls93, 74ls175, 74ls181, 74ls374, 74ls670, 74lv157, DM74ls173, sn74ls244, sn5470, 4024bc
- PR #591: Cleaned up misplaced subcircuits — moved
CA3020,LM108,LM3080,MC1496,NE556,TL03xA,UA702Mfrom a duplicate location into the canonicallibrary/SubcircuitLibrary/path - Subcircuit files from
SUBCKT/directory moved tolibrary/SubcircuitLibrary/(June 2026)
- Added a Microwatt NGHDL co-simulation example in
nghdl/Example/demonstrating mixed-signal simulation with the open-source Microwatt POWER ISA soft-core processor (via PR #569)
- Added
libreadline-devto the Dockerfile to resolve a build failure on newer Ubuntu base images
- Fixed workspace newline handling issue (PR #469)
eSim is licensed under the GNU General Public License v3.0. See LICENSE for details.
Built with ❤️ by the FOSSEE Team at IIT Bombay
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