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Add digital IP blocks - #17

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padhmanethrri wants to merge 8 commits into
FOSSEE:Digital-Verilog-IPsfrom
padhmanethrri:padhma_ip
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Add digital IP blocks#17
padhmanethrri wants to merge 8 commits into
FOSSEE:Digital-Verilog-IPsfrom
padhmanethrri:padhma_ip

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Purpose

Added digital IP blocks developed using Verilog through the NgVeri feature of eSim, as part of the FOSSEE eSim Summer Fellowship 2026.

IPs Included

  • CRC-8 Generator
  • Elastic Buffer (CDC FIFO)
  • Frequency Comparator
  • Hamming Distance Accumulator
  • LFSR
  • Razor Flip-Flop
  • Scan Chain Controller FSM
  • Sorter (4-input)

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@padhmanethrri