Add ESP32 PARLIO-capable boards (C5/C6/H2/P4) with required ISR-IRAM flags

[zackees]

Summary

• Add the two required PARLIO TX ISR build flags (CONFIG_PARLIO_TX_ISR_HANDLER_IN_IRAM=1 and CONFIG_PARLIO_TX_ISR_CACHE_SAFE=1) to every ESP32 chip whose SoC capabilities expose PARLIO: C5, C6, H2, P4.
• Add a new platforms/platformio.esp32p4.ini env (the P4 was completely missing).
• Bump the pioarduino platform-package on the C5/C6/H2 envs to 55.03.35 for consistency with the newly added P4 env.
• Add a comment block next to the flags pointing future maintainers at FastLED src/platforms/esp/32/drivers/parlio/ as the canonical PARLIO-capable chipset list.

Why

Without these flags the FastLED PARLIO driver's TX ISR sits in flash and takes cache-miss stalls during execution, silently corrupting LED protocol timing. The FastLED driver only signals their absence with a compile-time #warning, which is easy to miss.

Boards explicitly NOT modified

S3 / C3 / C2 / S2 / original-ESP32 envs are intentionally left without the PARLIO flags — those chips don't have the PARLIO peripheral (SOC_PARLIO_SUPPORTED=0) and adding the flags would falsely imply they do.

Test plan

• pio run -c platforms/platformio.esp32c5.ini succeeds
• pio run -c platforms/platformio.esp32c6.ini succeeds
• pio run -c platforms/platformio.esp32h2.ini succeeds
• pio run -c platforms/platformio.esp32p4.ini succeeds
• Confirm the FastLED PARLIO #warning no longer fires on these envs

Closes#9

🤖 Generated with Claude Code

Summary by CodeRabbit

• New Features

  • Added support for ESP32-P4 development board

• Chores

  • Updated platform toolchains for ESP32-C5, ESP32-C6, and ESP32-H2 boards
  • Improved system performance optimization for LED interface across all ESP32 variants

[coderabbitai]

Caution

Review failed

The pull request is closed.

ℹ️ Recent review info

⚙️ Run configuration

Configuration used: defaults

Review profile: CHILL

Plan: Pro

Run ID: c9dc5e6e-3c36-4dd3-b0ea-e976f53fb9ee

📥 Commits

Reviewing files that changed from the base of the PR and between ac5ed12 and 0b8e6c0.

📒 Files selected for processing (4)

• platforms/platformio.esp32c5.ini
• platforms/platformio.esp32c6.ini
• platforms/platformio.esp32h2.ini
• platforms/platformio.esp32p4.ini

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📝 Walkthrough

Walkthrough

Three existing PlatformIO environments (esp32c5, esp32c6, esp32h2) are updated to platform-espressif32 version 55.03.35 and gain CONFIG_PARLIO_TX_ISR_HANDLER_IN_IRAM=1 and CONFIG_PARLIO_TX_ISR_CACHE_SAFE=1 build flags. A new platformio.esp32p4.ini file is added with equivalent configuration for the ESP32-P4 board.

Changes

PARLIO ISR flags and platform updates across PARLIO-capable ESP32 envs

Layer / File(s)	Summary
Platform bump + PARLIO build flags for esp32c5, esp32c6, esp32h2 platforms/platformio.esp32c5.ini, platforms/platformio.esp32c6.ini, platforms/platformio.esp32h2.ini	Bumps platform-espressif32 to 55.03.35 in all three envs and adds CONFIG_PARLIO_TX_ISR_HANDLER_IN_IRAM=1 and CONFIG_PARLIO_TX_ISR_CACHE_SAFE=1 with comments noting these apply only to PARLIO-capable chips. esp32c6 additionally gains board_build.partitions = huge_app.csv and merges its USB CDC flags into the expanded build_flags block.
New esp32p4 environment platforms/platformio.esp32p4.ini	Adds a complete PlatformIO config for ESP32-P4: pinned platform URL, esp32-p4-evboard board, Arduino framework, huge_app.csv partitions, PARLIO ISR build flags, ARDUINO_USB_MODE=1, and FastLED lib dependency.

Estimated code review effort

🎯 2 (Simple) | ⏱️ ~10 minutes

Possibly related issues

• esp32: CONFIG_PARLIO_TX_ISR_HANDLER_IN_IRAM=1 should be a boards.py default on all PARLIO-capable boards FastLED#3271: This PR directly implements the fix described in that issue by adding CONFIG_PARLIO_TX_ISR_HANDLER_IN_IRAM=1 and CONFIG_PARLIO_TX_ISR_CACHE_SAFE=1 to all four PARLIO-capable boards (esp32c5, esp32c6, esp32h2, esp32p4) that were identified as missing these flags.
• boards.py: derive PARLIO-capable board list from SOC_PARLIO_SUPPORTED, not a hand-maintained list FastLED#3304: This PR manually applies the same PARLIO ISR build flags that issue #3304 proposed deriving automatically from a parlio_capable field in ci/boards.py, covering the same four boards (esp32c5, esp32c6, esp32h2, esp32p4).

Poem

🐇 Hop hop, the PARLIO flags are here,
Four boards now safe from cache-miss fear!
C5, C6, H2, P4 — all aligned,
IRAM handlers neatly defined.
No LED timing lost in flash stalls tonight,
The rabbit stamped the .ini right! 🌟

✨ Finishing Touches

🧪 Generate unit tests (beta)

• Create PR with unit tests
• Commit unit tests in branch feat/esp32-parlio-boards

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