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Hithaishisr/README.md

👋 Hey, I'm Hithaishi S R

Aspiring VLSI Design & Verification Engineer currently sharpening my skills at Maven Silicon.
With a foundation in Electronics & Telecommunication Engineering, I'm diving deep into the world of chip design and digital verification — and loving every moment of it.

My toolkit includes Verilog, SystemVerilog, and UVM, along with industry-standard tools like Synopsys Design Compiler and Siemens QuestaSim.
But I don't stop there — when I'm not working on RTL and testbenches, you'll find me tinkering with ESP32, building IoT systems, and bringing hardware-software ideas to life.

💡 What I'm Into

  • 🧠 VLSI Design & Functional Verification
  • 🧪 Writing RTL code, testbenches & exploring UVM
  • 📡 Embedded Systems & Internet of Things (IoT)
  • 🚴 Cycling through winding ghat roads — the real stress buster
  • 🔧 Solving real-world problems with a mix of hardware + code

🛠️ Skills & Tools

  • Languages: Verilog, SystemVerilog, Embedded C, C/C++, Java (for Android)
  • Tools: Synopsys DC, Siemens QuestaSim, Xilinx ISE, Arduino IDE, Proteus, LTSpice
  • Tech Stack: RTL Design, Functional Verification, UVM, ESP32, HC-05, Serial Comm, Bluetooth, Wi-Fi

📌 Projects

Check out some of the things I've built:

I'm a "learn-by-doing" kinda person, always on the lookout for projects that challenge me and help me grow.
Let’s build something awesome — together or solo, I'm down! 🚀

Popular repositories Loading

  1. verification-of-apb-based-uart-master-core verification-of-apb-based-uart-master-corePublic

    UVM-based functional verification of an APB-based UART Master Core RTL. Includes multi-agent environment, assertions, coverage collection, and multiple test scenarios (full/half duplex, parity, fra…

    SystemVerilog 14 1

  2. Hithaishisr HithaishisrPublic

    1

  3. Iot-smart-home-automation Iot-smart-home-automationPublic

    IoT-based Smart Home Automation project to control 8 AC appliances and a smart door using ESP32 via Touch, Bluetooth, and Cloud with custom Android app.

    Java

  4. verilog-vault-100 verilog-vault-100Public

    Verilog

  5. verilog-designs-and-testbenches verilog-designs-and-testbenchesPublic

    A repository of Verilog RTL modules and testbenches, showcasing different digital design concepts and FSM implementations.

    Verilog

  6. Router-1x3 Router-1x3Public

    A Verilog RTL design of a 1x3 packet router with a complete UVM testbench for verification. Includes FIFO buffers, FSM control, assertions, coverage, and synthesis support.

    JavaScript