UCI register fencing for turbo speed support

[JC-000]

Summary

• Add LDA UCI_STATUS bus fence after every STA to UCI_CONTROL or UCI_CMD_DATA across the UCI backend. At turbo speeds (4-48 MHz) the 6502 writes registers faster than the FPGA can latch them, causing double-writes and command corruption. The read forces the bus cycle to complete before the next write.
• 11 fences total: 8 in src/net/uci/uci_cmd.s (uci_abort, uci_begin_cmd, uci_put_byte, uci_push_wait, uci_check_err CLR_ERR, uci_drain_resp, uci_drain_status, uci_ack) and 3 in src/net/uci/net.s (hostname write loop, null terminator, send data loop).
• Cost: 4 CPU cycles per fenced write, regardless of clock speed. No logic changes, no new control flow.

Test plan

• make BACKEND=uci builds cleanly (no new warnings)
• make (ip65 backend) still builds cleanly — no regressions
• Test A: HTTP GET at 1 MHz on U64E hardware (baseline, not yet passing due to pre-existing boot timing issue)
• Test B: HTTP GET at 48 MHz on U64E hardware (turbo validation)

🤖 Generated with Claude Code

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Originally posted by @JC-000 on 2026-04-16

[JC-000]

Originally posted by @JC-000 on 2026-04-17

Superseded by PR #20 which uses a delay-loop fence instead of LDA UCI_STATUS. The STATUS-read approach broke the UCI init sequence; the delay loop works at all speeds 1-48 MHz.