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feat(crypto): comb-accelerated onchip profile — 31.0 s handshake @64 MHz - #62

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Jul 21, 2026
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feat(crypto): comb-accelerated onchip profile — 31.0 s handshake @64 MHz#62
JC-000 merged 1 commit into
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feat/nistcurves-comb

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Adopts the comb-accelerated u1·G path on top of the v0.6.0 onchip profile, per the follow-up noted in #62's predecessor (#61).

Measurements (C64U)

config16324864 MHzDC
v0.6.0 onchip (no-comb)88.343.330.922.9 s1.1 s1396 MHz·s
v0.6.0 onchip+comb49.424.916.512.4 s~0.2 s787 MHz·s
  • HTTPS e2e: 38.4 s @48 / 31.0 s @64 — day's arc at 64 MHz: 64.7 → 47.5 → 39.7 → 31.0 s. First configuration at the edge of the 10–30 s real-server window.
  • REU-profile crossover drops to ~7 MHz; comb dominates no-comb onchip at every clock.
  • Verify is no longer the bottleneck (12.4 s of a 31.0 s handshake) — the non-verify half (X25519, SHA-256 transcript, record I/O, firmware latency) is the next profiling target.

Integration

  • USE_NISTCURVES_ONCHIP_COMB=1 (implies onchip): archive composed from upstream's full onchip archive trimmed to the P-256 comb set; ec_precompute_256 boot pass (REU bank 2 anchors); in-tree no-comb ec_scalar_mul shim gated out.
  • New cfg/c64-https-uci-onchip.cfg variant (documented deltas): ro segments + LIMLEE → CRYPTO_OVERLAY (CRYPTO_HOT had 29 B slack; COLD_SHADOW is flush-full). Default/onchip-no-comb builds keep the base cfg untouched.
  • Boot cost: precompute is ~50 s @64 MHz (~40 min at stock) — bench/e2e/KAT scripts grew C64_INIT_WAIT/C64_INIT_TIMEOUT, and the bench now boots at the first sweep speed instead of inheriting leftover device config.

Correctness

  • VICE KAT oracle 3/3 through the full comb chain (boot precompute → bank-2 anchors → Lim-Lee u1·G → CAVP verdicts); all hardware runs oracle-gated PASS.
  • One e2e attempt hit the known #137 link flake (retry passed) — unrelated to this change.

🤖 Generated with Claude Code

https://claude.ai/code/session_01UZmMaxyyykvYbCvJAc4QVW

USE_NISTCURVES_ONCHIP_COMB=1 (implies USE_NISTCURVES_ONCHIP): consume
the sibling's comb ecdsa256 + points256_comb + Lim-Lee data (composed
from the full onchip archive, trimmed to the P-256 set), add the
ec_precompute_256 boot pass (REU bank 2 $0000-$3FFF anchors, SPEC
§8.5), and gate out the in-tree no-comb ec_scalar_mul shim under the
flag. CRYPTO_HOT can't absorb the +1.1 KB comb code (29 B slack), so
the profile uses cfg/c64-https-uci-onchip.cfg — a documented variant
that moves RODATA/CRYPTO_RODATA/P256_RODATA + the new LIMLEE segment
into the free CRYPTO_OVERLAY (COLD_SHADOW is flush-full).
Boot cost: ec_precompute_256 is ~50 s at 64 MHz / ~3.5 min at 16 /
~40 min at stock — bench + e2e scripts grew C64_INIT_WAIT and the
bench now boots at the first sweep speed (it used to inherit leftover
device config). KAT script grew C64_INIT_TIMEOUT for the same reason.
Measured (C64U): verify 49.4/24.9/16.5/12.4 s at 16/32/48/64 MHz
(D~0.2 s, C=787 MHz*s); REU-profile crossover drops to ~7 MHz; comb
dominates no-comb onchip at every clock. HTTPS e2e: 38.4 s @48,
**31.0 s @64** — at the top edge of the 10-30 s real-server window.
VICE KAT oracle 3/3 (precompute + comb u1*G path); all hardware runs
oracle-gated.
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01UZmMaxyyykvYbCvJAc4QVW
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