docs: U64E ECDSA sweep — device delta vs C64U is REU DMA only

[JC-000]

Summary

Closes the owed U64E lane of the 2026-07-20 turbo-profile benchmark campaign. Ran the identical sweep protocol (tools/uci/bench_ecdsa_u64e.py, RFC 6979 vector file, n=2 medians) on the U64E at 16/32/48 MHz (the U64E has no 64 MHz enum) for all three nistcurves-v0.6.0 profiles at HEAD. 72/72 runs correctness-PASS. Documentation-only change: adds the U64E table + analysis to the "ECDSA P-256 verify wall-clock" section of CLAUDE.md.

Results (RFC 6979 medians, fits T(f)=D+C/f)

config	16 MHz	32 MHz	48 MHz	D (floor)	C
v0.6.0 REU	81.6 s	65.2 s	59.2 s	48.2 s	535 MHz·s
v0.6.0 onchip	87.6 s	44.9 s	30.5 s	2.0 s	1370 MHz·s
v0.6.0 onchip+comb	49.1 s	24.6 s	18.4 s	2.2 s	747 MHz·s

Device delta vs C64U at the same clocks

• REU profile: U64E +10–13% slower at every clock (floor 48.2 s vs 41.8 s) — consistent with the previously observed 82.1 vs 73.0 s e2e handshake split at 48 MHz.
• onchip profile: parity (−1.3% to +3.6%, within n=2 noise) at all three clocks.
• Conclusion: the U64E/C64U performance difference is entirely REU/expansion-bus DMA in the FPGA core; the CPU-bound path is device-independent.
• Comb is at parity at 16/32 MHz but +12% at 48 MHz (18.4 vs 16.5 s) — plausibly its Lim-Lee table fetches from REU bank 2 (DMA share grows with clock), flagged in the doc for an n>2 re-measure before leaning on it.
• U64E crossovers vs the REU profile shift down (higher REU floor): onchip ~18 MHz, comb ~5 MHz (C64U: ~22 / ~7).

Test plan

• 3 profiles × 3 clocks × 8 runs on real U64E hardware (10.53.21.158's sibling at 10.43.23.81), DeviceLock-queued, boot-at-speed
• All 72 runs returned the expected verify result (positive + tampered vectors)
• Fit residuals ≤0.4% (REU/onchip), ≤3.8% (comb)

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