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Jonathan-Moradi/README.md

Hi, I'm Yonatan Moradi 👋

🎓 4th-year Electrical Engineering Student @ HIT
💼 Hardware V&V Engineer @ Elbit Systems
⚡ Specializing in VLSI, Chip Design & Embedded Systems Email LinkedIn

📌 Featured Projects

Project Description Tech
⚡ Low-Power CDC DSP FIR filter + async CDC FIFO + UART with clock-gated power controller Verilog
🔲 16-bit Processor Custom ISA with ALU, Control Unit & FSM Verilog
🔁 DMA Controller Bus Master with FSM & memory management VHDL

🔧 Tech Stack

HDL & FPGA Verilog VHDL ModelSim Quartus Prime

Embedded & Systems C C++ Python Raspberry Pi ROS2 MAVLink

Protocols UART SPI I2C USB TCP/IP

Lab Equipment Oscilloscope Spectrum Analyzer Logic Analyzer Signal Generator

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  1. Low-Power-CDC-DSP Low-Power-CDC-DSP Public

    A low-power DSP system featuring an asynchronous FIFO with CDC between 100MHz and 10MHz domains.

  2. 16-bit-processor-verilog 16-bit-processor-verilog Public

    16-bit processor implemented in Verilog with custom ISA, ALU, Control Unit and FSM-based instruction execution.

    Verilog

  3. dma-controller-vhdl dma-controller-vhdl Public

    DMA Controller implemented in VHDL — Bus Master with FSM-based memory transfer logic.

    VHDL