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1. IEEE-754-32-bit-Floating-Point-Subtraction-Verilog IEEE-754-32-bit-Floating-Point-Subtraction-VerilogPublic

   This project implements a single-precision IEEE-754 floating-point subtraction unit using Verilog HDL. It performs sign handling, exponent alignment, mantissa subtraction, and result normalization.…

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2. Sales-Forecasting-for-Retail Sales-Forecasting-for-RetailPublic

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3. 32-bit-ALU-Design-and-Functional-Verification-Verilog 32-bit-ALU-Design-and-Functional-Verification-VerilogPublic

   RTL design and functional verification of a 32-bit ALU using Verilog HDL. Supports arithmetic, logical, and shift operations with corner-case handling such as divide-by-zero, underflow, and tri-sta…

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