Skip to content
View Merinyeldho's full-sized avatar
🎯
Focusing
🎯
Focusing

    Block or report Merinyeldho

    Block user

    Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

    You must be logged in to block users.

    Maximum 250 characters. Please don’t include any personal information such as legal names or email addresses. Markdown is supported. This note will only be visible to you.
    Report abuse

    Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

    Report abuse

    Pinned Loading

    1. Low-Power-and-Area-Efficient-Carry-Select-Adder-CSLA-Low-Power-and-Area-Efficient-Carry-Select-Adder-CSLA-Public

      Verilog implementation modified carry select adder

      Verilog 3

    2. SAP1-computer-verilogSAP1-computer-verilogPublic

      Verilog implementation of SAP-1 computer architecture

      Verilog 1

    3. Multilingo-TranslatorMultilingo-TranslatorPublic

      Translator

      Python