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[Common] Support scaled & clamped swiglu, srelu for BF16 - #3132
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Greptile SummaryThis PR adds new CUDA kernels (
Confidence Score: 5/5The change is purely additive — new source files, a new public header section, and new tests — with no modifications to existing kernels or data paths. The math is correct and the forward/backward formulas are consistent with each other and with the test references. All new launch code is guarded by early-return dimension checks and type-dispatch macros; the reduction kernel uses correct smem sizing bounded by kReductionThreads. The one finding (ClampedSwiGLU reference hardcoding alpha) is a test-coverage concern rather than a runtime bug. test_scaled_activation.cu: the ClampedSwiGLU backward reference should explicitly thread kClampedAlpha through qgelu/dqgelu calls rather than relying on the 1.702f default. Important Files Changed
Reviews (9): Last reviewed commit: "[pre-commit.ci] auto fixes from pre-comm..." | Re-trigger Greptile |
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zhongbozhu
commented
Jun 16, 2026
/te-ci pytorch |
vthumbe1503
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LGTM. Left minor comments
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| * kernels with nvec=1, i.e. regular elementwise loads/stores. | ||
| */ | ||
| #include <transformer_engine/activation.h> |
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A general comment - I think that limiting this to only FP32/FP16 is not needed and you could very
easily have tensor-scaled FP8 support here.
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I agree but it's gonna be challenging to extend to blockwise scaling (when it comes to GLU interleaved gated activation, and non-gated activation should be fine), and I do think that for fp8 fp4, we do expect a fused gemm to be built so it's directly fused into the GEMM epilogue.
Signed-off-by: zhongboz <zhongboz@nvidia.com>
Signed-off-by: Zhongbo Zhu <zhongboz@nvidia.com>
Signed-off-by: Zhongbo Zhu <zhongboz@nvidia.com>
Signed-off-by: Zhongbo Zhu <zhongboz@nvidia.com>
for more information, see https://pre-commit.ci
Signed-off-by: vthumbe1503 <vthumbe@nvidia.com>
60e5ecb to
c8c19a9CompareSigned-off-by: Zhongbo Zhu <zhongboz@nvidia.com>
Signed-off-by: Zhongbo Zhu <zhongboz@nvidia.com>
Signed-off-by: Varun Thumbe <vthumbe@nvidia.com>
Signed-off-by: Varun Thumbe <vthumbe@nvidia.com>
for more information, see https://pre-commit.ci
Signed-off-by: Varun Thumbe <vthumbe@nvidia.com>
Signed-off-by: Varun Thumbe <vthumbe@nvidia.com>
for more information, see https://pre-commit.ci
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vthumbe1503
commented
Jul 14, 2026
/te-ci |
Signed-off-by: Varun Thumbe <vthumbe@nvidia.com>
for more information, see https://pre-commit.ci
vthumbe1503
commented
Jul 14, 2026
/te-ci |
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Description
Support Mega-C++ with Cublas BF16 Grouped GEMM backend: #3099
Kernel Perf:



Fixes # (issue)
Type of change
Changes
Please list the changes introduced in this PR:
Checklist: