Design Verification · IC Design · RTL · FPGA
Mission: I build engineering portfolios that are easy to verify: runnable source code, structured testbenches, assertions that catch real violations, measurable coverage and reproducible simulation results.
I am pursuing a career as a Design Verification Engineer. My electronics and telecommunications background helps me approach hardware systems from RISC-V microarchitecture and AMBA bus protocols to comprehensive UVM verification workflows.
name: Van Dinh Namtarget_role: Design Verification Engineerfocus:
- SystemVerilog, UVM, SVA, constrained-random testing
- scoreboard, monitor, functional coverage, regression, waveform debug
- AMBA APB4, AXI4-Lite, protocol compliance
- Verilog RTL, RISC-V RV32I pipeline, MMIO, AES acceleratortools:
- Synopsys VCS, Verdi, QuestaSim, ModelSim, Quartus
- Python, C, shell scripting| Repository | Technical evidence | Why it matters |
|---|---|---|
| apb4-uvm-lab | APB4 slave, sequence item, constrained-random sequence, driver, monitor, scoreboard, coverage and QuestaSim scripts | Compact end-to-end UVM lab that is easy to run and review |
| axi4-lite-uvm-lab | AXI4-Lite master/slave RTL, five AW/W/B/AR/R channels, reactive driver, SVA and regression | Demonstrates verification of independent handshake channels |
| systemverilog-sva-protocol-checkers | APB4 assertions, positive tests and intentional negative tests | Shows an assertion catching the PENABLE requires PSEL violation |
| apb4-axi4-uvm-verification-portfolio | UVM architecture, scenario matrix, scoreboard flow, assertion checklist and coverage strategy | Public overview of a protocol verification methodology |
| RISC-V Pipeline with AES | CPU pipeline, AES MMIO, UART bootloader, unit tests, UVM regression, waveforms and Quartus flow | Main proof of RTL integration, verification and FPGA prototyping |
| Graduation Project Documentation | IP architecture, QuestaSim guide, waveforms, Quartus synthesis and FPGA bring-up | Technical documentation for a fast project review |
| EFR32xG21 AHT20 Monitor | Non-blocking firmware, BLE, UART and sensor integration | Adds embedded systems and device communication experience |
Random Sequence → Driver → APB4 DUT → Monitor → Scoreboard
└──────→ Coverage
Validated with QuestaSim 10.2c:
APB4_UVM_LAB_PASS checks=43
| Property | Purpose |
|---|---|
penable_requires_psel | The access phase must not occur before the slave is selected |
setup_advances_to_access | The setup phase must advance to the access phase |
control_stable_while_waiting | Control signals must remain stable while waiting for PREADY |
control_known_when_selected | Control signals must not contain unknown values |
Simulation output:
APB4_SVA_POSITIVE_TEST_PASS
APB4 violation: PENABLE requires PSEL
The FPGA SoC integrates a 32-bit RISC-V pipeline with IF/ID/EX/MEM/WB stages, forwarding, load-use stall handling, branch/jump flush logic, register-file writeback, an MMIO path, an AES accelerator and a UART bootloader.
| Verification target | Result |
|---|---|
| Tested RISC-V instructions | 39 |
| Random ISA checks | 700 |
| CPU-AES end-to-end vectors | 50 |
| AES UVM random regression | PASS |
| CPU UVM end-to-end regression | PASS |
| MMIO functional coverage | 100% |
- Run APB4 UVM Lab to inspect the constrained-random flow and scoreboard.
- Run AXI4-Lite UVM Lab to inspect independent handshake-channel handling.
- Run the positive and negative tests in SVA Protocol Checkers to see assertions detect violations.
- Open RISC-V Pipeline with AES to review RTL, UVM regression and the FPGA workflow.
I am interested in opportunities in Design Verification, RTL Verification, IC Design and FPGA engineering.
Specification → stimulus → coverage → debug → proof.
SystemVerilog · UVM · SVA · APB4 · AXI4-Lite · RTL · FPGA