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hundeboll/fpga ofs dev n5010 #4

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fcc6aff
pci: add Silicom Denmark vendor id
hundeboll-silicom Feb 1, 2021
f17ccaa
fpga: dfl: pci: add device id for Silicom N5010 PAC card
hundeboll-silicom Feb 1, 2021
64650b0
fpga: dfl-spi-altera: support n1050 feature revision
hundeboll-silicom Feb 1, 2021
d971697
mfd: intel-m10-bmc: add n5010 variant
hundeboll-silicom Feb 1, 2021
caac97a
hwmon: intel-m10-bmc-hwmon: add n5010 sensors
hundeboll-silicom Feb 1, 2021
deb6305
fpga: intel-m10-bmc-secure: add n5010 device id
hundeboll-silicom Feb 1, 2021
e2d20c2
fpga: dfl: implement dfl_dev_get_base_dev()
hundeboll-silicom Feb 1, 2021
a545747
net: ethernet: silicom: add n5010-phy driver
hundeboll-silicom Feb 1, 2021
449696c
net: ethernet: silicom: add n5010-hssi driver
hundeboll-silicom Feb 1, 2021
b063472
configs: add n5010 defconfig snippet
hundeboll-silicom Feb 1, 2021
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7 changes: 7 additions & 0 deletions MAINTAINERS
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Original file line number Diff line number Diff line change
Expand Up @@ -16242,6 +16242,13 @@ S: Maintained
F: drivers/input/touchscreen/silead.c
F: drivers/platform/x86/touchscreen_dmi.c

SILICOM PAC N5010 DRIVER
M: Esa Leskinen <ele@silicom.dk>
L: netdev@vger.kernel.org
S: Maintained
F: drivers/net/ethernet/silicom/n5010-hssi.c
F: drivers/net/ethernet/silicom/n5010-phy.c

SILICON LABS WIRELESS DRIVERS (for WFxxx series)
M: Jérôme Pouiller <jerome.pouiller@silabs.com>
S: Supported
Expand Down
33 changes: 33 additions & 0 deletions configs/n5010_defconfig
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Original file line number Diff line number Diff line change
@@ -0,0 +1,33 @@
CONFIG_FPGA_DFL=m
CONFIG_FPGA_DFL_FME=m
CONFIG_FPGA_DFL_FME_MGR=m
CONFIG_FPGA_DFL_FME_BRIDGE=m
CONFIG_FPGA_DFL_FME_REGION=m
CONFIG_FPGA_DFL_AFU=m
CONFIG_FPGA_DFL_SPI_ALTERA=m
CONFIG_FPGA_DFL_PCI=m

CONFIG_FPGA_VFIO_MDEV_DFL=m

CONFIG_FPGA=m
CONFIG_FPGA_MGR=m
CONFIG_FPGA_BRIDGE=m
CONFIG_FPGA_REGION=m
CONFIG_FPGA_SEC_MGR=m
CONFIG_IFPGA_M10_BMC_SECURE=m

CONFIG_SPI=y
CONFIG_SPI_MASTER=y
CONFIG_MFD_INTEL_M10_BMC=m
CONFIG_SENSORS_INTEL_M10_BMC_HWMON=m

CONFIG_SPI_ALTERA=m

CONFIG_FIXED_PHY=m
CONFIG_NET_VENDOR_SILICOM=y
CONFIG_N5010_HSSI=m
CONFIG_n5010_PHY=m

CONFIG_REGMAP_MMIO=m
CONFIG_REGMAP_INDIRECT_REGISTER=m
CONFIG_REGMAP_SPI_AVMM=m
3 changes: 3 additions & 0 deletions drivers/fpga/dfl-pci.c
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Expand Up @@ -67,6 +67,8 @@ static void cci_pci_free_irq(struct pci_dev *pcidev)
#define PCIE_DEVICE_ID_INTEL_PAC_N3000 0x0B30
#define PCIE_DEVICE_ID_INTEL_PAC_D5005 0x0B2B
#define PCIE_DEVCIE_ID_INTEL_OFS 0xaf00
#define PCIE_DEVICE_ID_SILICOM_PAC_N5010 0x1000

/* VF Device */
#define PCIE_DEVICE_ID_VF_INT_5_X 0xBCBF
#define PCIE_DEVICE_ID_VF_INT_6_X 0xBCC1
Expand All @@ -84,6 +86,7 @@ static struct pci_device_id cci_pcie_id_tbl[] = {
{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_INTEL_PAC_D5005),},
{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_INTEL_PAC_D5005_VF),},
{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVCIE_ID_INTEL_OFS),},
{PCI_DEVICE(PCI_VENDOR_ID_SILICOM_DENMARK, PCIE_DEVICE_ID_SILICOM_PAC_N5010),},
{0,}
};
MODULE_DEVICE_TABLE(pci, cci_pcie_id_tbl);
Expand Down
19 changes: 16 additions & 3 deletions drivers/fpga/dfl-spi-altera.c
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Expand Up @@ -22,6 +22,11 @@
#include <linux/spi/altera.h>
#include <linux/dfl.h>

#include "dfl.h"

#define FME_FEATURE_ID_MAX10_SPI 0xe
#define FME_FEATURE_REV_MAX10_SPI_N5010 0x1

struct dfl_altera_spi {
void __iomem *base;
struct regmap *regmap;
Expand Down Expand Up @@ -117,6 +122,13 @@ static struct spi_board_info m10_bmc_info = {
.chip_select = 0,
};

static struct spi_board_info m10_n5010_bmc_info = {
.modalias = "m10-n5010",
.max_speed_hz = 12500000,
.bus_num = 0,
.chip_select = 0,
};

static struct platform_device *create_cntrl(struct device *dev,
void __iomem *base,
struct spi_board_info *m10_info)
Expand Down Expand Up @@ -180,7 +192,10 @@ static int dfl_spi_altera_probe(struct dfl_device *dfl_dev)
if (IS_ERR(aspi->regmap))
return PTR_ERR(aspi->regmap);

aspi->altr_spi = create_cntrl(dev, aspi->base, &m10_bmc_info);
if (dfl_feature_revision(aspi->base) == FME_FEATURE_REV_MAX10_SPI_N5010)

@trixirt trixirt Feb 1, 2021

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Is this unique enough ?
What happens if n3000 revs this feature

@fpgamatt fpgamatt Feb 1, 2021

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n3000 uses a different driver, dfl-n3000-nios.c

@hundeboll-silicom hundeboll-silicom Feb 2, 2021

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We did start out with a dedicated n5010 feature id, but changed it to a feature revision after preliminary review from Russ.

@trixirt trixirt Feb 3, 2021

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what i mean is the {feature id, revision} unique for all cards ? it would see that checking if this was a 5010 card by its pci id was better than checking the revision of a feature a lot of cards share

@fpgamatt fpgamatt Feb 3, 2021

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I believe I was the person who suggested a different revision to distinguish the target of the SPI connection. The hardware connected to the DFL bus is the same for the d5005 and the n5010, but the other end of the SPI connection is slightly different. I suggested just bumping the revision because the hardware interface didn't change.

I hadn't thought about using the PCIe device id to distinguish the target of the SPI, but I think that is the wrong approach. DFLs can exist on non-PCIe devices; so writing a DFL driver that depends on a PCIe device ID breaks the layering.

aspi->altr_spi = create_cntrl(dev, aspi->base, &m10_n5010_bmc_info);
else
aspi->altr_spi = create_cntrl(dev, aspi->base, &m10_bmc_info);

if (IS_ERR(aspi->altr_spi)) {
dev_err(dev, "%s failed to create spi platform driver\n",
Expand All @@ -198,8 +213,6 @@ static void dfl_spi_altera_remove(struct dfl_device *dfl_dev)
platform_device_unregister(aspi->altr_spi);
}

#define FME_FEATURE_ID_MAX10_SPI 0xe

static const struct dfl_device_id dfl_spi_altera_ids[] = {
{ FME_ID, FME_FEATURE_ID_MAX10_SPI },
{ }
Expand Down
9 changes: 9 additions & 0 deletions drivers/fpga/dfl.c
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Expand Up @@ -487,6 +487,15 @@ EXPORT_SYMBOL(dfl_driver_unregister);

#define is_header_feature(feature) ((feature)->id == FEATURE_ID_FIU_HEADER)

struct device *dfl_dev_get_base_dev(struct dfl_device *dfl_dev)
{
if (!dfl_dev || !dfl_dev->cdev)
return NULL;

return dfl_dev->cdev->parent;
}
EXPORT_SYMBOL(dfl_dev_get_base_dev);

/**
* dfl_fpga_dev_feature_uinit - uinit for sub features of dfl feature device
* @pdev: feature device.
Expand Down
4 changes: 4 additions & 0 deletions drivers/fpga/intel-m10-bmc-secure.c
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Expand Up @@ -792,6 +792,10 @@ static const struct platform_device_id intel_m10bmc_secure_ids[] = {
.name = "d5005bmc-secure",
.driver_data = (unsigned long)M10_D5005,
},
{
.name = "n5010bmc-secure",
.driver_data = (unsigned long)M10_N5010,
},
{ }
};

Expand Down
116 changes: 116 additions & 0 deletions drivers/hwmon/intel-m10-bmc-hwmon.c
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Expand Up @@ -228,6 +228,118 @@ static const struct m10bmc_hwmon_board_data d5005bmc_hwmon_bdata = {
.hinfo = d5005bmc_hinfo,
};

static const struct m10bmc_sdata n5010bmc_temp_tbl[] = {
{ 0x100, 0x0, 0x104, 0x0, 0x0, 1000, "Board Local Temperature" },
{ 0x108, 0x0, 0x10c, 0x0, 0x0, 1000, "FPGA 1 Temperature" },
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{ 0x110, 0x0, 0x114, 0x0, 0x0, 1000, "FPGA 2 Temperature" },
{ 0x118, 0x0, 0x0, 0x0, 0x0, 1000, "Card Top Temperature" },
{ 0x11c, 0x0, 0x0, 0x0, 0x0, 1000, "Card Bottom Temperature" },
{ 0x128, 0x0, 0x0, 0x0, 0x0, 1000, "FPGA 1.2V Temperature" },
{ 0x134, 0x0, 0x0, 0x0, 0x0, 1000, "FPGA 5V Temperature" },
{ 0x140, 0x0, 0x0, 0x0, 0x0, 1000, "FPGA 0.9V Temperature" },
{ 0x14c, 0x0, 0x0, 0x0, 0x0, 1000, "FPGA 0.85V Temperature" },
{ 0x158, 0x0, 0x0, 0x0, 0x0, 1000, "AUX 12V Temperature" },
{ 0x164, 0x0, 0x0, 0x0, 0x0, 1000, "Backplane 12V Temperature" },
{ 0x1a8, 0x0, 0x0, 0x0, 0x0, 1000, "QSFP28-1 Temperature" },
{ 0x1ac, 0x0, 0x0, 0x0, 0x0, 1000, "QSFP28-2 Temperature" },
{ 0x1b0, 0x0, 0x0, 0x0, 0x0, 1000, "QSFP28-3 Temperature" },
{ 0x1b4, 0x0, 0x0, 0x0, 0x0, 1000, "QSFP28-4 Temperature" },
{ 0x1b8, 0x0, 0x0, 0x0, 0x0, 1000, "CVL1 Internal Temperature" },
{ 0x1bc, 0x0, 0x0, 0x0, 0x0, 1000, "CVL2 Internal Temperature" },
};

static const struct m10bmc_sdata n5010bmc_in_tbl[] = {
{ 0x120, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 1.2V Voltage" },
{ 0x12c, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 5V Voltage" },
{ 0x138, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 0.9V Voltage" },
{ 0x144, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 0.85V Voltage" },
{ 0x150, 0x0, 0x0, 0x0, 0x0, 1, "AUX 12V Voltage" },
{ 0x15c, 0x0, 0x0, 0x0, 0x0, 1, "Backplane 12V Voltage" },
{ 0x16c, 0x0, 0x0, 0x0, 0x0, 1, "DDR4 1.2V Voltage" },
{ 0x17c, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 1.8V Voltage" },
{ 0x184, 0x0, 0x0, 0x0, 0x0, 1, "QDR 1.3V Voltage" },
{ 0x18c, 0x0, 0x0, 0x0, 0x0, 1, "CVL1 0.8V Voltage" },
{ 0x194, 0x0, 0x0, 0x0, 0x0, 1, "CVL1 1.05V Voltage" },
{ 0x19c, 0x0, 0x0, 0x0, 0x0, 1, "CVL2 1.05V Voltage" },
{ 0x1a4, 0x0, 0x0, 0x0, 0x0, 1, "CVL2 0.8V Voltage" },
};

static const struct m10bmc_sdata n5010bmc_curr_tbl[] = {
{ 0x124, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 1.2V Current" },
{ 0x130, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 5V Current" },
{ 0x13c, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 0.9V Current" },
{ 0x148, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 0.85V Current" },
{ 0x154, 0x0, 0x0, 0x0, 0x0, 1, "AUX 12V Current" },
{ 0x160, 0x0, 0x0, 0x0, 0x0, 1, "Backplane 12V Current" },
{ 0x168, 0x0, 0x0, 0x0, 0x0, 1, "DDR4 1.2V Current" },
{ 0x178, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 1.8V Current" },
{ 0x180, 0x0, 0x0, 0x0, 0x0, 1, "QDR 1.3V Current" },
{ 0x188, 0x0, 0x0, 0x0, 0x0, 1, "CVL1 0.8V Current" },
{ 0x190, 0x0, 0x0, 0x0, 0x0, 1, "CVL1 1.05V Current" },
{ 0x198, 0x0, 0x0, 0x0, 0x0, 1, "CVL2 1.05V Current" },
{ 0x1a0, 0x0, 0x0, 0x0, 0x0, 1, "CVL2 0.8V Current" },
};

static const struct hwmon_channel_info *n5010bmc_hinfo[] = {
HWMON_CHANNEL_INFO(temp,
HWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_LABEL,
HWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_LABEL,
HWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_LABEL,
HWMON_T_INPUT | HWMON_T_LABEL,
HWMON_T_INPUT | HWMON_T_LABEL,
HWMON_T_INPUT | HWMON_T_LABEL,
HWMON_T_INPUT | HWMON_T_LABEL,
HWMON_T_INPUT | HWMON_T_LABEL,
HWMON_T_INPUT | HWMON_T_LABEL,
HWMON_T_INPUT | HWMON_T_LABEL,
HWMON_T_INPUT | HWMON_T_LABEL,
HWMON_T_INPUT | HWMON_T_LABEL,
HWMON_T_INPUT | HWMON_T_LABEL,
HWMON_T_INPUT | HWMON_T_LABEL,
HWMON_T_INPUT | HWMON_T_LABEL,
HWMON_T_INPUT | HWMON_T_LABEL,
HWMON_T_INPUT | HWMON_T_LABEL),
HWMON_CHANNEL_INFO(in,
HWMON_I_INPUT | HWMON_I_LABEL,
HWMON_I_INPUT | HWMON_I_LABEL,
HWMON_I_INPUT | HWMON_I_LABEL,
HWMON_I_INPUT | HWMON_I_LABEL,
HWMON_I_INPUT | HWMON_I_LABEL,
HWMON_I_INPUT | HWMON_I_LABEL,
HWMON_I_INPUT | HWMON_I_LABEL,
HWMON_I_INPUT | HWMON_I_LABEL,
HWMON_I_INPUT | HWMON_I_LABEL,
HWMON_I_INPUT | HWMON_I_LABEL,
HWMON_I_INPUT | HWMON_I_LABEL,
HWMON_I_INPUT | HWMON_I_LABEL,
HWMON_I_INPUT | HWMON_I_LABEL),
HWMON_CHANNEL_INFO(curr,
HWMON_C_INPUT | HWMON_C_LABEL,
HWMON_C_INPUT | HWMON_C_LABEL,
HWMON_C_INPUT | HWMON_C_LABEL,
HWMON_C_INPUT | HWMON_C_LABEL,
HWMON_C_INPUT | HWMON_C_LABEL,
HWMON_C_INPUT | HWMON_C_LABEL,
HWMON_C_INPUT | HWMON_C_LABEL,
HWMON_C_INPUT | HWMON_C_LABEL,
HWMON_C_INPUT | HWMON_C_LABEL,
HWMON_C_INPUT | HWMON_C_LABEL,
HWMON_C_INPUT | HWMON_C_LABEL,
HWMON_C_INPUT | HWMON_C_LABEL,
HWMON_C_INPUT | HWMON_C_LABEL),
NULL
};

static const struct m10bmc_hwmon_board_data n5010bmc_hwmon_bdata = {
.tables = {
[hwmon_temp] = n5010bmc_temp_tbl,
[hwmon_in] = n5010bmc_in_tbl,
[hwmon_curr] = n5010bmc_curr_tbl,
},

.hinfo = n5010bmc_hinfo,
};

static umode_t
m10bmc_hwmon_is_visible(const void *data, enum hwmon_sensor_types type,
u32 attr, int channel)
Expand Down Expand Up @@ -438,6 +550,10 @@ static const struct platform_device_id intel_m10bmc_hwmon_ids[] = {
.name = "d5005bmc-hwmon",
.driver_data = (unsigned long)&d5005bmc_hwmon_bdata,
},
{
.name = "n5010bmc-hwmon",
.driver_data = (unsigned long)&n5010bmc_hwmon_bdata,
},
{ }
};

Expand Down
11 changes: 11 additions & 0 deletions drivers/mfd/intel-m10-bmc.c
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Expand Up @@ -41,6 +41,12 @@ static struct mfd_cell m10bmc_pacn3000_subdevs[] = {
{ .name = "n3000bmc-secure" },
};

static struct mfd_cell m10bmc_n5010_bmc_subdevs[] = {
{ .name = "n5010bmc-hwmon" },
{ .name = "n5010bmc-secure" },
{ .name = "n5010bmc-phy" },
};

static const struct regmap_range n3000_fw_handshake_regs[] = {
regmap_reg_range(M10BMC_TELEM_START, M10BMC_TELEM_END),
};
Expand Down Expand Up @@ -293,6 +299,10 @@ static int intel_m10_bmc_spi_probe(struct spi_device *spi)
cells = m10bmc_bmc_subdevs;
n_cell = ARRAY_SIZE(m10bmc_bmc_subdevs);
break;
case M10_N5010:
cells = m10bmc_n5010_bmc_subdevs;
n_cell = ARRAY_SIZE(m10bmc_n5010_bmc_subdevs);
break;
default:
return -ENODEV;
}
Expand All @@ -308,6 +318,7 @@ static int intel_m10_bmc_spi_probe(struct spi_device *spi)
static const struct spi_device_id m10bmc_spi_id[] = {
{ "m10-n3000", M10_N3000 },
{ "m10-d5005", M10_D5005 },
{ "m10-n5010", M10_N5010 },
{ }
};
MODULE_DEVICE_TABLE(spi, m10bmc_spi_id);
Expand Down
1 change: 1 addition & 0 deletions drivers/net/ethernet/Kconfig
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Expand Up @@ -167,6 +167,7 @@ source "drivers/net/ethernet/seeq/Kconfig"
source "drivers/net/ethernet/sfc/Kconfig"
source "drivers/net/ethernet/sgi/Kconfig"
source "drivers/net/ethernet/silan/Kconfig"
source "drivers/net/ethernet/silicom/Kconfig"

@rweight rweight Jan 29, 2021

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Should this change (and the corresponding Makefile change) be in the previous phy patch, since that is where the silicom sub-directory directory is created?

source "drivers/net/ethernet/sis/Kconfig"
source "drivers/net/ethernet/smsc/Kconfig"
source "drivers/net/ethernet/socionext/Kconfig"
Expand Down
1 change: 1 addition & 0 deletions drivers/net/ethernet/Makefile
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Expand Up @@ -78,6 +78,7 @@ obj-$(CONFIG_NET_VENDOR_ROCKER) += rocker/
obj-$(CONFIG_NET_VENDOR_SAMSUNG) += samsung/
obj-$(CONFIG_NET_VENDOR_SEEQ) += seeq/
obj-$(CONFIG_NET_VENDOR_SILAN) += silan/
obj-$(CONFIG_NET_VENDOR_SILICOM) += silicom/
obj-$(CONFIG_NET_VENDOR_SIS) += sis/
obj-$(CONFIG_NET_VENDOR_SOLARFLARE) += sfc/
obj-$(CONFIG_NET_VENDOR_SGI) += sgi/
Expand Down
37 changes: 37 additions & 0 deletions drivers/net/ethernet/silicom/Kconfig
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@@ -0,0 +1,37 @@
# SPDX-License-Identifier: GPL-2.0-only
#
# Silicom network device configuration
#

config NET_VENDOR_SILICOM
bool "Silicom devices"
default y
help
If you have a network (Ethernet) card belonging to this class, say Y.

Note that the answer to this question doesn't directly affect the
kernel: saying N will just cause the configurator to skip all
the questions about Silicom cards. If you say Y, you will be asked for
your specific card in the following questions.

if NET_VENDOR_SILICOM

config N5010_PHY
tristate "Fixed Phy Driver for Silicom PAC N5010"
depends on MFD_INTEL_M10_BMC && FIXED_PHY
help
The n5010 card consists of a primary FPGA running the network controller,
and a side-fpga running the board management controller (bmc). This driver
reads status bits and controls link LEDs via the bmc.

config N5010_HSSI
tristate "Control Plane Driver for Silicom PAC N5010 HSSI"
select N5010_PHY
select REGMAP_INDIRECT_REGISTER
help
This driver provides control plane support for the Silicom N5010
Programmable Acceleration Card. This driver adds network interfaces
for the line-side QFSP modules, supporting various control/status
operations.

endif # NET_VENDOR_SILICOM
7 changes: 7 additions & 0 deletions drivers/net/ethernet/silicom/Makefile
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@@ -0,0 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
#
# Makefile for the Silicom network device drivers.
#

obj-$(CONFIG_N5010_PHY) += n5010-phy.o
obj-$(CONFIG_N5010_HSSI) += n5010-hssi.o
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