NutShell master branch re-adaption for FPGA platforms

[zhangziqing]

The master branch of NutShell can not generate an FPGA project that provides correct functionality(#205#204#200 ). Therefore I made serval changes to the NutShell and the FPGA project tcl.

1. For software simulation, NutShell uses the nutcoretrap in CSR as a signal to dump the statistic during the simulation, this signal is connected by the boringUtil. However, the source of this connection is missing when using the FPGA platform. I set nutcoretrap signal to zero when using FPGA.
2. Vivado can automatically identify the signals for AXI protocol if the name of these signals follow a certain form, the early version of NutShell uses a sed command in Makefile to convert the Chisel name to the specific form of AXI Signals. However, after using --spilt-verilog option, not all the signals were converted by the command.
3. Still an issue related to the --spilt-verilog, vivado project tcl only adds TopMain.v to the project, therefore other RTL source files are missing in the vivado project.
4. The tcl file generated by vivado restricts the version of vivado to 2019.1. However, these restrictions are not needed. I modified the tcl file, currently the mismatch of vivado version will only cause a warning message other than a termination to the project generation.
5. The FPGA platform uses a top name different from the simulation. Current Makefile needs to use mv command to rename the top file name from SimTop.sv to TopMain.sv, which will cause an error to the FPGA platform as the `SimTop.sv`` does not exist.
6. Currently Nutshell uses LogPerfHelper for logging. this module connects all the log units to the control logic in SimTop, which does not exist in the FPGA project. So I have disabled logging for the FPGA platform

The issues mentioned above have been resolved in the pull request. These modifications have been tested with sidewinder and PYNQ.

[poemonsense]

Look good to me

@sashimi-yzh Do you have time to take a look?

[poemonsense]

Thank you for the contribution.

Please help add a CI test (simply build the verilog from Chisel?) for FPGA verilog to .github/workflows/main.yml if possible.

[poemonsense]

I'm merging this now.

If there're issues after yzh review, we can further fix them