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Pull request overview
This PR applies low-level SDMA fast-path micro-optimizations in include/mori/cco/cco.hpp to improve instruction selection and memory coalescing for queue packet publishing on AMDGPU targets.
Changes:
- Introduces an internal
impl::global()helper to force global address space accesses for SDMA queue-related loads/stores and HIP atomics. - Reworks
ccoSdmaUnitwrites to use 16-byte vector stores (Uint4) for better coalescing when writing COPY/ATOMIC packets into the ring.
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jhchouuu
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Tested on both arches — gfx950 (MI355X) and gfx1250 — with the baseline at the merge-base 624002c8 and identical build flags for both trees.
Correctness. The seven CCO SDMA tests (put, get, put_mt, block, edge, signal, warp_issue) in fork mode pass on both trees: 8/8 ranks on gfx950, 4/4 on gfx1250.
ISA. Both claims hold, and identically on the two arches (test_sdma_put):
| flat_load | flat_store | flat_atomic | global_load | global_store | |
|---|---|---|---|---|---|
| base | 100 | 84 | 12 | 4 | 0 |
| PR | 6 | 0 | 12 | 102 | 72 |
Packet stores go from three per unit to two. The baseline emits dwordx3@0 + dwordx4@offset:12 + dword@offset:28 — note offset 12 is not 16B-aligned — where this PR emits dwordx4@0 + dwordx4@offset:16. Same shape on gfx1250 with b96/b32/b128.
Perf. 8 B put, thread scope, quiet completion, 2 ranks, runs interleaved to cancel drift:
- gfx950: median 6.076 → 5.970 us (-1.7%), and the PR is faster in 8 of 9 paired runs.
- gfx1250: no measurable difference. Base-first ordering says "PR 0.5% slower", PR-first ordering says "PR 1.5% faster" — the sign follows run order, so an ordering artifact dominates. Pooling both blocks, so each binary ran first 9 times and second 9 times: 8.207 → 8.147 us, well inside the 7.98–8.60 spread.
Bandwidth is unchanged on both: 57.0 GB/s at 8 MB on gfx950, 980 GB/s at 8 MB on gfx1250.
The obvious gfx1250 worry — whether moving packet stores from flat to global could break "packet dwords land before the doorbell" — does not apply. ccoSdmaPublishStores() is a release fence at agent scope there, and s_waitcnt(0) on gfx9; neither relies on flat bumping an extra counter.
Comments inline, nothing blocking.
| // Implicit cast to global memory space. | ||
| template <typename T, typename T2 = typename std::remove_volatile<T>::type> | ||
| __device__ __host__ inline static T2* global(T* ptr) { | ||
| return (T2*)(T2 CCO_GLOBAL_SPACE*)reinterpret_cast<uintptr_t>(ptr); |
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This reinterpret_cast<uintptr_t> looks like it could be simplified to a plain address-space cast. It cannot, and I would suggest a comment saying so — it is the most deletable-looking line in the PR, and deleting it silently undoes the entire change while every test still passes.
I tried it. Replacing the body with
return (T2*)(T2 CCO_GLOBAL_SPACE*)ptr;and regenerating the device assembly for test_sdma_put (gfx950, same flags) puts everything back on flat:
| as written | direct cast | |
|---|---|---|
| flat_load_dwordx2 / x4 | 6 / 0 | 68 / 32 |
| flat_store_dwordx2 / x4 | 0 / 0 | 48 / 24 |
| global_load + global_store | 174 | 4 |
addrspacecast (addrspacecast p to as(1)) to as(0) is an inverse pair that gets folded away immediately, so the address space never survives to InferAddressSpaces. inttoptr cannot be folded, which is precisely why the round trip works. sgpr_count is 44 either way, so nothing is being paid for it.
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yes it is tricky.. atomic_load/store builtin functions do not accept pointers with non-default memory space, that's why this workaround was necessary
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Thanks for taking a look! I am going to be away until 17.09, so I guess we can put this PR on hold. |
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