All issues

`sie` read is not masked by `mideleg`: non-delegated `mie` enable bits are visible to S-mode

#43

· CacheGuruinthemaking opened

on Sep 8, 2026

Vectored trap target is computed as `xtvec & (4*cause - 4)` due to operator precedence; cause 1 vectors to address 0

#42

· CacheGuruinthemaking opened

on Sep 8, 2026

`sstatus` write takes SPP from bit 7 instead of bit 8

#41

· CacheGuruinthemaking opened

on Sep 8, 2026

Synchronous exception priority follows ascending cause code instead of the spec priority table

#40

· CacheGuruinthemaking opened

on Sep 8, 2026

Big-endian data accesses: loads are not byte-swapped while stores are, so a store/load round-trip corrupts data when `mstatus.UBE`/`MBE`/`SBE` is set

#39

· AnonymousHippo90324 opened

on Sep 6, 2026

Exception delegation uses `st_prv_o >= PRV_S`: M-mode exceptions are delegated to S-mode and U-mode exceptions never are

#38

· AnonymousHippo90324 opened

on Sep 6, 2026

Interrupt taken in M-mode is delivered to the S-mode handler; interrupt cause codes and `mideleg` are compared in the wrong encoding

#37

· AnonymousHippo90324 opened

on Sep 6, 2026

medeleg is never driven on RV32 with S-mode: MEDELEG writes are ignored and exception delegation is undefined

#36

· AnonymousHippo90324 opened

on Sep 6, 2026

Issue with forwarding path from LD instruction followed by ADD

#35

· nguyen-vu-axiomise opened

on Dec 11, 2025

Any detailed description about "Fast, precise interrupts"?

#32

· jhqian opened

on Jun 16, 2025

Linux compatibility

#29

· JOHNTBIJU opened

on Nov 7, 2021

Debug Control

#28

· abdallah250 opened

on Oct 13, 2021