Name		Name	Last commit message	Last commit date
rtl/verilog		rtl/verilog
.gitignore		.gitignore
LICENSE.txt		LICENSE.txt
README.md		README.md
_config.yml		_config.yml

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memory

Generic memory implementations

Parameterized, synthesizable memories targetting:

FPGAs
eASIC technology

License

Released under a modified BSD style license.

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Generic memory implementations

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