aes: detect AES-NI + SSSE3 for AES-CTR by tarcieri · Pull Request #214 · RustCrypto/block-ciphers

tarcieri · 2020-12-02T17:28:44Z

The accelerated AES-CTR implementation in this crate makes use of SSSE3 instructions.

Though in theory all CPUs with AES-NI should have SSSE3, the aes target feature does not implicitly enable SSSE3 per the Rust Reference:

https://doc.rust-lang.org/reference/attributes/codegen.html#x86-or-x86_64

...so this separate check ensures the availability of SSSE3.

The accelerated AES-CTR implementation in this crate makes use of SSSE3 instructions. Though in theory all CPUs with AES-NI should have SSSE3, the `aes` target feature does not implicitly enable SSSE3 per the Rust Reference: https://doc.rust-lang.org/reference/attributes/codegen.html#x86-or-x86_64 ...so this separate check ensures the availability of SSSE3.

tarcieri · 2020-12-02T17:28:44Z

The accelerated AES-CTR implementation in this crate makes use of SSSE3 instructions.

Though in theory all CPUs with AES-NI should have SSSE3, the aes target feature does not implicitly enable SSSE3 per the Rust Reference:

https://doc.rust-lang.org/reference/attributes/codegen.html#x86-or-x86_64

...so this separate check ensures the availability of SSSE3.

The accelerated AES-CTR implementation in this crate makes use of SSSE3 instructions. Though in theory all CPUs with AES-NI should have SSSE3, the `aes` target feature does not implicitly enable SSSE3 per the Rust Reference: https://doc.rust-lang.org/reference/attributes/codegen.html#x86-or-x86_64 ...so this separate check ensures the availability of SSSE3.

tarcieri · 2020-12-02T17:28:44Z

The accelerated AES-CTR implementation in this crate makes use of SSSE3 instructions.

Though in theory all CPUs with AES-NI should have SSSE3, the aes target feature does not implicitly enable SSSE3 per the Rust Reference:

https://doc.rust-lang.org/reference/attributes/codegen.html#x86-or-x86_64

...so this separate check ensures the availability of SSSE3.

The accelerated AES-CTR implementation in this crate makes use of SSSE3 instructions. Though in theory all CPUs with AES-NI should have SSSE3, the `aes` target feature does not implicitly enable SSSE3 per the Rust Reference: https://doc.rust-lang.org/reference/attributes/codegen.html#x86-or-x86_64 ...so this separate check ensures the availability of SSSE3.

tarcieri · 2020-12-02T17:28:44Z

The accelerated AES-CTR implementation in this crate makes use of SSSE3 instructions.

Though in theory all CPUs with AES-NI should have SSSE3, the aes target feature does not implicitly enable SSSE3 per the Rust Reference:

https://doc.rust-lang.org/reference/attributes/codegen.html#x86-or-x86_64

...so this separate check ensures the availability of SSSE3.

The accelerated AES-CTR implementation in this crate makes use of SSSE3 instructions. Though in theory all CPUs with AES-NI should have SSSE3, the `aes` target feature does not implicitly enable SSSE3 per the Rust Reference: https://doc.rust-lang.org/reference/attributes/codegen.html#x86-or-x86_64 ...so this separate check ensures the availability of SSSE3.

tarcieri · 2020-12-02T17:28:44Z

The accelerated AES-CTR implementation in this crate makes use of SSSE3 instructions.

Though in theory all CPUs with AES-NI should have SSSE3, the aes target feature does not implicitly enable SSSE3 per the Rust Reference:

https://doc.rust-lang.org/reference/attributes/codegen.html#x86-or-x86_64

...so this separate check ensures the availability of SSSE3.

The accelerated AES-CTR implementation in this crate makes use of SSSE3 instructions. Though in theory all CPUs with AES-NI should have SSSE3, the `aes` target feature does not implicitly enable SSSE3 per the Rust Reference: https://doc.rust-lang.org/reference/attributes/codegen.html#x86-or-x86_64 ...so this separate check ensures the availability of SSSE3.

tarcieri · 2020-12-02T17:28:44Z

The accelerated AES-CTR implementation in this crate makes use of SSSE3 instructions.

Though in theory all CPUs with AES-NI should have SSSE3, the aes target feature does not implicitly enable SSSE3 per the Rust Reference:

https://doc.rust-lang.org/reference/attributes/codegen.html#x86-or-x86_64

...so this separate check ensures the availability of SSSE3.

The accelerated AES-CTR implementation in this crate makes use of SSSE3 instructions. Though in theory all CPUs with AES-NI should have SSSE3, the `aes` target feature does not implicitly enable SSSE3 per the Rust Reference: https://doc.rust-lang.org/reference/attributes/codegen.html#x86-or-x86_64 ...so this separate check ensures the availability of SSSE3.

tarcieri · 2020-12-02T17:28:44Z

The accelerated AES-CTR implementation in this crate makes use of SSSE3 instructions.

Though in theory all CPUs with AES-NI should have SSSE3, the aes target feature does not implicitly enable SSSE3 per the Rust Reference:

https://doc.rust-lang.org/reference/attributes/codegen.html#x86-or-x86_64

...so this separate check ensures the availability of SSSE3.

The accelerated AES-CTR implementation in this crate makes use of SSSE3 instructions. Though in theory all CPUs with AES-NI should have SSSE3, the `aes` target feature does not implicitly enable SSSE3 per the Rust Reference: https://doc.rust-lang.org/reference/attributes/codegen.html#x86-or-x86_64 ...so this separate check ensures the availability of SSSE3.

tarcieri · 2020-12-02T17:28:44Z

The accelerated AES-CTR implementation in this crate makes use of SSSE3 instructions.

Though in theory all CPUs with AES-NI should have SSSE3, the aes target feature does not implicitly enable SSSE3 per the Rust Reference:

https://doc.rust-lang.org/reference/attributes/codegen.html#x86-or-x86_64

...so this separate check ensures the availability of SSSE3.

The accelerated AES-CTR implementation in this crate makes use of SSSE3 instructions. Though in theory all CPUs with AES-NI should have SSSE3, the `aes` target feature does not implicitly enable SSSE3 per the Rust Reference: https://doc.rust-lang.org/reference/attributes/codegen.html#x86-or-x86_64 ...so this separate check ensures the availability of SSSE3.