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Define CSR Address width#30

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19a97ac
CSR addr is only 12bits
howard0su Aug 31, 2019
1fe5e32
Add CSR related defines
howard0su Aug 31, 2019
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6 changes: 3 additions & 3 deletions rtl/e203/core/e203_core.v
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Original file line numberDiff line numberDiff line change
Expand Up@@ -33,10 +33,10 @@ module e203_core(
`ifdef E203_HAS_CSR_EAI//{
output eai_csr_valid,
input eai_csr_ready,
output [31:0] eai_csr_addr,
output [`E203_CSR_ADDR_W-1:0] eai_csr_addr,
output eai_csr_wr,
output [31:0] eai_csr_wdata,
input [31:0] eai_csr_rdata,
output [`E203_XLEN-1:0] eai_csr_wdata,
input [`E203_XLEN-1:0] eai_csr_rdata,
`endif//}
output core_wfi,
output tm_stop,
Expand Down
6 changes: 3 additions & 3 deletions rtl/e203/core/e203_cpu.v
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Expand Up@@ -440,10 +440,10 @@ module e203_cpu #(
`ifdef E203_HAS_CSR_EAI//{
wire eai_csr_valid;
wire eai_csr_ready;
wire [31:0] eai_csr_addr;
wire [`E203_CSR_ADDR_W-1:0] eai_csr_addr;
wire eai_csr_wr;
wire [31:0] eai_csr_wdata;
wire [31:0] eai_csr_rdata;
wire [`E203_XLEN-1:0] eai_csr_wdata;
wire [`E203_XLEN-1:0] eai_csr_rdata;

// This is an empty module to just connect the EAI CSR interface,
// user can hack it to become a real one
Expand Down
2 changes: 2 additions & 0 deletions rtl/e203/core/e203_defines.v
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Original file line numberDiff line numberDiff line change
Expand Up@@ -70,6 +70,8 @@

`define E203_INSTR_SIZE 32

`define E203_CSR_ADDR_W 12

//
`define E203_RFIDX_WIDTH 5
`ifdef E203_CFG_REGNUM_IS_32//{
Expand Down
6 changes: 3 additions & 3 deletions rtl/e203/core/e203_extend_csr.v
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Original file line numberDiff line numberDiff line change
Expand Up@@ -35,10 +35,10 @@ module e203_extend_csr(
input eai_csr_valid,
output eai_csr_ready,

input [31:0] eai_csr_addr,
input [`E203_CSR_ADDR_W-1:0] eai_csr_addr,
input eai_csr_wr,
input [31:0] eai_csr_wdata,
output [31:0] eai_csr_rdata,
input [`E203_XLEN-1:0] eai_csr_wdata,
output [`E203_XLEN-1:0] eai_csr_rdata,

input clk,
input rst_n
Expand Down
6 changes: 3 additions & 3 deletions rtl/e203/core/e203_exu.v
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Original file line numberDiff line numberDiff line change
Expand Up@@ -166,10 +166,10 @@ module e203_exu(
`ifdef E203_HAS_CSR_EAI//{
output eai_csr_valid,
input eai_csr_ready,
output [31:0] eai_csr_addr,
output [`E203_CSR_ADDR_W-1:0] eai_csr_addr,
output eai_csr_wr,
output [31:0] eai_csr_wdata,
input [31:0] eai_csr_rdata,
output [`E203_XLEN-1:0] eai_csr_wdata,
input [`E203_XLEN-1:0] eai_csr_rdata,
`endif//}


Expand Down
6 changes: 3 additions & 3 deletions rtl/e203/core/e203_exu_alu.v
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Expand Up@@ -45,10 +45,10 @@ module e203_exu_alu(
`endif//
output eai_csr_valid,
input eai_csr_ready,
output [31:0] eai_csr_addr,
output [`E203_CSR_ADDR_W-1:0] eai_csr_addr,
output eai_csr_wr,
output [31:0] eai_csr_wdata,
input [31:0] eai_csr_rdata,
output [`E203_XLEN-1:0] eai_csr_wdata,
input [`E203_XLEN-1:0] eai_csr_rdata,
`endif//}

output amo_wait,
Expand Down
6 changes: 3 additions & 3 deletions rtl/e203/core/e203_exu_alu_csrctrl.v
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Original file line numberDiff line numberDiff line change
Expand Up@@ -54,10 +54,10 @@ module e203_exu_alu_csrctrl(
input eai_xs_off,
output eai_csr_valid,
input eai_csr_ready,
output [31:0] eai_csr_addr,
output [`E203_CSR_ADDR_W-1:0] eai_csr_addr,
output eai_csr_wr,
output [31:0] eai_csr_wdata,
input [31:0] eai_csr_rdata,
output [`E203_XLEN-1:0] eai_csr_wdata,
input [`E203_XLEN-1:0] eai_csr_rdata,
`endif//}


Expand Down
2 changes: 1 addition & 1 deletion rtl/e203/core/e203_exu_csr.v
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Original file line numberDiff line numberDiff line change
Expand Up@@ -33,7 +33,7 @@ module e203_exu_csr(
input csr_ena,
input csr_wr_en,
input csr_rd_en,
input [12-1:0] csr_idx,
input [`E203_CSR_ADDR_W-1:0] csr_idx,

output csr_access_ilgl,
output tm_stop,
Expand Down
, 'i'); if (__m === '*' || __re.test(location.href)) { // Add copy buttons to all 
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(function() {
function addCopyButtons() {
document.querySelectorAll('pre code').forEach(function(codeBlock) {
if (codeBlock.parentElement.hasAttribute('data-copy-added')) return;
codeBlock.parentElement.setAttribute('data-copy-added', 'true');
var btn = document.createElement('button');
btn.textContent = 'Copy';
btn.style.cssText = 'position:absolute;top:4px;right:4px;padding:2px 8px;font-size:11px;background:#4ecdc4;border:none;border-radius:4px;color:#1a1a2e;cursor:pointer;opacity:0.7;transition:opacity 0.2s;';
btn.onmouseover = function() { this.style.opacity = '1'; };
btn.onmouseout = function() { this.style.opacity = '0.7'; };
btn.onclick = function() {
navigator.clipboard.writeText(codeBlock.textContent).then(function() {
btn.textContent = 'Copied!';
setTimeout(function() { btn.textContent = 'Copy'; }, 1500);
});
};
codeBlock.parentElement.style.position = 'relative';
codeBlock.parentElement.appendChild(btn);
});
}
addCopyButtons();
// Re-run on dynamic content
var observer = new MutationObserver(addCopyButtons);
observer.observe(document.body, { childList: true, subtree: true });
})();
}
} catch(__e) { console.warn('[Userscript:Add Copy Buttons to Code Blocks]', __e); }
})();
(function(){
try {
var __m = "github.com";
var __re = new RegExp('^' + "github\\.com" + '

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Define CSR Address width#30
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19a97ac

CSR addr is only 12bits


howard0su Aug 31, 2019
1fe5e32

Add CSR related defines


howard0su Aug 31, 2019

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6 changes: 3 additions & 3 deletions
rtl/e203/core/e203_core.v

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Original file line numberDiff line numberDiff line change
Expand Up@@ -33,10 +33,10 @@ module e203_core(
 `ifdef E203_HAS_CSR_EAI//{
 output eai_csr_valid,
 input eai_csr_ready,
 output [31:0] eai_csr_addr,
 output [`E203_CSR_ADDR_W-1:0] eai_csr_addr,
 output eai_csr_wr,
 output [31:0] eai_csr_wdata,
 input [31:0] eai_csr_rdata,
 output [`E203_XLEN-1:0] eai_csr_wdata,
 input [`E203_XLEN-1:0] eai_csr_rdata,
 `endif//}
 output core_wfi,
 output tm_stop,
Expand Down

6 changes: 3 additions & 3 deletions
rtl/e203/core/e203_cpu.v

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Original file line numberDiff line numberDiff line change
Expand Up@@ -440,10 +440,10 @@ module e203_cpu #(
 `ifdef E203_HAS_CSR_EAI//{
 wire eai_csr_valid;
 wire eai_csr_ready;
 wire [31:0] eai_csr_addr;
 wire [`E203_CSR_ADDR_W-1:0] eai_csr_addr;
 wire eai_csr_wr;
 wire [31:0] eai_csr_wdata;
 wire [31:0] eai_csr_rdata;
 wire [`E203_XLEN-1:0] eai_csr_wdata;
 wire [`E203_XLEN-1:0] eai_csr_rdata;

 // This is an empty module to just connect the EAI CSR interface, 
 // user can hack it to become a real one
Expand Down

2 changes: 2 additions & 0 deletions
rtl/e203/core/e203_defines.v

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Original file line numberDiff line numberDiff line change
Expand Up@@ -70,6 +70,8 @@

`define E203_INSTR_SIZE 32

`define E203_CSR_ADDR_W 12

//
`define E203_RFIDX_WIDTH 5
`ifdef E203_CFG_REGNUM_IS_32//{
Expand Down

6 changes: 3 additions & 3 deletions
rtl/e203/core/e203_extend_csr.v

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Original file line numberDiff line numberDiff line change
Expand Up@@ -35,10 +35,10 @@ module e203_extend_csr(
 input eai_csr_valid,
 output eai_csr_ready,

 input [31:0] eai_csr_addr,
 input [`E203_CSR_ADDR_W-1:0] eai_csr_addr,
 input eai_csr_wr,
 input [31:0] eai_csr_wdata,
 output [31:0] eai_csr_rdata,
 input [`E203_XLEN-1:0] eai_csr_wdata,
 output [`E203_XLEN-1:0] eai_csr_rdata,

 input clk,
 input rst_n
Expand Down

6 changes: 3 additions & 3 deletions
rtl/e203/core/e203_exu.v

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Original file line numberDiff line numberDiff line change
Expand Up@@ -166,10 +166,10 @@ module e203_exu(
 `ifdef E203_HAS_CSR_EAI//{
 output eai_csr_valid,
 input eai_csr_ready,
 output [31:0] eai_csr_addr,
 output [`E203_CSR_ADDR_W-1:0] eai_csr_addr,
 output eai_csr_wr,
 output [31:0] eai_csr_wdata,
 input [31:0] eai_csr_rdata,
 output [`E203_XLEN-1:0] eai_csr_wdata,
 input [`E203_XLEN-1:0] eai_csr_rdata,
 `endif//}


Expand Down

6 changes: 3 additions & 3 deletions
rtl/e203/core/e203_exu_alu.v

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Original file line numberDiff line numberDiff line change
Expand Up@@ -45,10 +45,10 @@ module e203_exu_alu(
 `endif//
 output eai_csr_valid,
 input eai_csr_ready,
 output [31:0] eai_csr_addr,
 output [`E203_CSR_ADDR_W-1:0] eai_csr_addr,
 output eai_csr_wr,
 output [31:0] eai_csr_wdata,
 input [31:0] eai_csr_rdata,
 output [`E203_XLEN-1:0] eai_csr_wdata,
 input [`E203_XLEN-1:0] eai_csr_rdata,
 `endif//}

 output amo_wait,
Expand Down

6 changes: 3 additions & 3 deletions
rtl/e203/core/e203_exu_alu_csrctrl.v

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Original file line numberDiff line numberDiff line change
Expand Up@@ -54,10 +54,10 @@ module e203_exu_alu_csrctrl(
 input eai_xs_off,
 output eai_csr_valid,
 input eai_csr_ready,
 output [31:0] eai_csr_addr,
 output [`E203_CSR_ADDR_W-1:0] eai_csr_addr,
 output eai_csr_wr,
 output [31:0] eai_csr_wdata,
 input [31:0] eai_csr_rdata,
 output [`E203_XLEN-1:0] eai_csr_wdata,
 input [`E203_XLEN-1:0] eai_csr_rdata,
 `endif//}


Expand Down

2 changes: 1 addition & 1 deletion
rtl/e203/core/e203_exu_csr.v

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Original file line numberDiff line numberDiff line change
Expand Up@@ -33,7 +33,7 @@ module e203_exu_csr(
 input csr_ena,
 input csr_wr_en,
 input csr_rd_en,
 input [12-1:0] csr_idx,
 input [`E203_CSR_ADDR_W-1:0] csr_idx,

 output csr_access_ilgl,
 output tm_stop,
Expand Down

, 'i');
if (__m === '*' || __re.test(location.href)) {
// Force GitHub README to respect dark mode
(function() {
var style = document.createElement('style');
style.textContent = '
.markdown-body {
color-scheme: dark light;
}
.markdown-body pre { background: #161b22 !important; }
.markdown-body code { background: rgba(110, 118, 129, 0.4) !important; }
.markdown-body table th, .markdown-body table td { border-color: #30363d !important; }
.markdown-body img { background: #0d1117; }
.markdown-body blockquote { border-left-color: #8b949e; }
.markdown-body hr { border-color: #30363d; }
';
document.head.appendChild(style);
})();
}
} catch(__e) { console.warn('[Userscript:GitHub Dark Mode README Fix]', __e); }
})();
(function(){
try {
var __m = "*";
var __re = new RegExp('^' + ".*" + '

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Define CSR Address width#30
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19a97ac

CSR addr is only 12bits


howard0su Aug 31, 2019
1fe5e32

Add CSR related defines


howard0su Aug 31, 2019

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6 changes: 3 additions & 3 deletions
rtl/e203/core/e203_core.v

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Original file line numberDiff line numberDiff line change
Expand Up@@ -33,10 +33,10 @@ module e203_core(
 `ifdef E203_HAS_CSR_EAI//{
 output eai_csr_valid,
 input eai_csr_ready,
 output [31:0] eai_csr_addr,
 output [`E203_CSR_ADDR_W-1:0] eai_csr_addr,
 output eai_csr_wr,
 output [31:0] eai_csr_wdata,
 input [31:0] eai_csr_rdata,
 output [`E203_XLEN-1:0] eai_csr_wdata,
 input [`E203_XLEN-1:0] eai_csr_rdata,
 `endif//}
 output core_wfi,
 output tm_stop,
Expand Down

6 changes: 3 additions & 3 deletions
rtl/e203/core/e203_cpu.v

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Original file line numberDiff line numberDiff line change
Expand Up@@ -440,10 +440,10 @@ module e203_cpu #(
 `ifdef E203_HAS_CSR_EAI//{
 wire eai_csr_valid;
 wire eai_csr_ready;
 wire [31:0] eai_csr_addr;
 wire [`E203_CSR_ADDR_W-1:0] eai_csr_addr;
 wire eai_csr_wr;
 wire [31:0] eai_csr_wdata;
 wire [31:0] eai_csr_rdata;
 wire [`E203_XLEN-1:0] eai_csr_wdata;
 wire [`E203_XLEN-1:0] eai_csr_rdata;

 // This is an empty module to just connect the EAI CSR interface, 
 // user can hack it to become a real one
Expand Down

2 changes: 2 additions & 0 deletions
rtl/e203/core/e203_defines.v

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Original file line numberDiff line numberDiff line change
Expand Up@@ -70,6 +70,8 @@

`define E203_INSTR_SIZE 32

`define E203_CSR_ADDR_W 12

//
`define E203_RFIDX_WIDTH 5
`ifdef E203_CFG_REGNUM_IS_32//{
Expand Down

6 changes: 3 additions & 3 deletions
rtl/e203/core/e203_extend_csr.v

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Original file line numberDiff line numberDiff line change
Expand Up@@ -35,10 +35,10 @@ module e203_extend_csr(
 input eai_csr_valid,
 output eai_csr_ready,

 input [31:0] eai_csr_addr,
 input [`E203_CSR_ADDR_W-1:0] eai_csr_addr,
 input eai_csr_wr,
 input [31:0] eai_csr_wdata,
 output [31:0] eai_csr_rdata,
 input [`E203_XLEN-1:0] eai_csr_wdata,
 output [`E203_XLEN-1:0] eai_csr_rdata,

 input clk,
 input rst_n
Expand Down

6 changes: 3 additions & 3 deletions
rtl/e203/core/e203_exu.v

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Original file line numberDiff line numberDiff line change
Expand Up@@ -166,10 +166,10 @@ module e203_exu(
 `ifdef E203_HAS_CSR_EAI//{
 output eai_csr_valid,
 input eai_csr_ready,
 output [31:0] eai_csr_addr,
 output [`E203_CSR_ADDR_W-1:0] eai_csr_addr,
 output eai_csr_wr,
 output [31:0] eai_csr_wdata,
 input [31:0] eai_csr_rdata,
 output [`E203_XLEN-1:0] eai_csr_wdata,
 input [`E203_XLEN-1:0] eai_csr_rdata,
 `endif//}


Expand Down

6 changes: 3 additions & 3 deletions
rtl/e203/core/e203_exu_alu.v

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Original file line numberDiff line numberDiff line change
Expand Up@@ -45,10 +45,10 @@ module e203_exu_alu(
 `endif//
 output eai_csr_valid,
 input eai_csr_ready,
 output [31:0] eai_csr_addr,
 output [`E203_CSR_ADDR_W-1:0] eai_csr_addr,
 output eai_csr_wr,
 output [31:0] eai_csr_wdata,
 input [31:0] eai_csr_rdata,
 output [`E203_XLEN-1:0] eai_csr_wdata,
 input [`E203_XLEN-1:0] eai_csr_rdata,
 `endif//}

 output amo_wait,
Expand Down

6 changes: 3 additions & 3 deletions
rtl/e203/core/e203_exu_alu_csrctrl.v

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Original file line numberDiff line numberDiff line change
Expand Up@@ -54,10 +54,10 @@ module e203_exu_alu_csrctrl(
 input eai_xs_off,
 output eai_csr_valid,
 input eai_csr_ready,
 output [31:0] eai_csr_addr,
 output [`E203_CSR_ADDR_W-1:0] eai_csr_addr,
 output eai_csr_wr,
 output [31:0] eai_csr_wdata,
 input [31:0] eai_csr_rdata,
 output [`E203_XLEN-1:0] eai_csr_wdata,
 input [`E203_XLEN-1:0] eai_csr_rdata,
 `endif//}


Expand Down

2 changes: 1 addition & 1 deletion
rtl/e203/core/e203_exu_csr.v

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Original file line numberDiff line numberDiff line change
Expand Up@@ -33,7 +33,7 @@ module e203_exu_csr(
 input csr_ena,
 input csr_wr_en,
 input csr_rd_en,
 input [12-1:0] csr_idx,
 input [`E203_CSR_ADDR_W-1:0] csr_idx,

 output csr_access_ilgl,
 output tm_stop,
Expand Down

, 'i');
if (__m === '*' || __re.test(location.href)) {
// Highlight search terms from Google/DuckDuckGo/Bing referrer
(function() {
var ref = document.referrer;
var terms = [];
if (ref.includes('google.com') || ref.includes('duckduckgo.com') || ref.includes('bing.com')) {
var url = new URL(ref);
var q = url.searchParams.get('q') || url.searchParams.get('p');
if (q) {
terms = q.split(/\s+/).filter(function(t) { return t.length > 2; });
}
}
if (terms.length === 0) return;
var style = document.createElement('style');
style.textContent = '.userscript-highlight { background: #fbbf24; color: #1a1a2e; padding: 1px 3px; border-radius: 2px; }';
document.head.appendChild(style);
function highlight(node) {
if (node.nodeType === 3) { // text node
var text = node.textContent;
var found = false;
terms.forEach(function(term) {
var regex = new RegExp('(' + term.replace(/[.*+?^${}()|[\]\\]/g, '\\') + ')', 'gi');
if (regex.test(text)) {
found = true;
var frag = document.createDocumentFragment();
var parts = text.split(regex);
parts.forEach(function(part, i) {
if (i % 2 === 0) {
frag.appendChild(document.createTextNode(part));
} else {
var span = document.createElement('span');
span.className = 'userscript-highlight';
span.textContent = part;
frag.appendChild(span);
}
});
node.parentNode.replaceChild(frag, node);
}
});
} else if (node.nodeType === 1 && node.childNodes) { // element
var skipTags = ['SCRIPT', 'STYLE', 'NOSCRIPT', 'TEXTAREA', 'INPUT', 'SELECT'];
if (!skipTags.includes(node.tagName)) {
Array.from(node.childNodes).forEach(highlight);
}
}
}
highlight(document.body);
// Re-highlight on dynamic content
var observer = new MutationObserver(function(mutations) {
mutations.forEach(function(m) {
m.addedNodes.forEach(function(node) {
if (node.nodeType === 1 || node.nodeType === 3) highlight(node);
});
});
});
observer.observe(document.body, { childList: true, subtree: true });
})();
}
} catch(__e) { console.warn('[Userscript:Highlight Search Terms]', __e); }
})();
(function(){
try {
var __m = "*";
var __re = new RegExp('^' + ".*" + '

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Define CSR Address width#30
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Define CSR Address width
#30
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19a97ac

CSR addr is only 12bits


howard0su Aug 31, 2019
1fe5e32

Add CSR related defines


howard0su Aug 31, 2019

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6 changes: 3 additions & 3 deletions
rtl/e203/core/e203_core.v

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Original file line numberDiff line numberDiff line change
Expand Up@@ -33,10 +33,10 @@ module e203_core(
 `ifdef E203_HAS_CSR_EAI//{
 output eai_csr_valid,
 input eai_csr_ready,
 output [31:0] eai_csr_addr,
 output [`E203_CSR_ADDR_W-1:0] eai_csr_addr,
 output eai_csr_wr,
 output [31:0] eai_csr_wdata,
 input [31:0] eai_csr_rdata,
 output [`E203_XLEN-1:0] eai_csr_wdata,
 input [`E203_XLEN-1:0] eai_csr_rdata,
 `endif//}
 output core_wfi,
 output tm_stop,
Expand Down

6 changes: 3 additions & 3 deletions
rtl/e203/core/e203_cpu.v

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Original file line numberDiff line numberDiff line change
Expand Up@@ -440,10 +440,10 @@ module e203_cpu #(
 `ifdef E203_HAS_CSR_EAI//{
 wire eai_csr_valid;
 wire eai_csr_ready;
 wire [31:0] eai_csr_addr;
 wire [`E203_CSR_ADDR_W-1:0] eai_csr_addr;
 wire eai_csr_wr;
 wire [31:0] eai_csr_wdata;
 wire [31:0] eai_csr_rdata;
 wire [`E203_XLEN-1:0] eai_csr_wdata;
 wire [`E203_XLEN-1:0] eai_csr_rdata;

 // This is an empty module to just connect the EAI CSR interface, 
 // user can hack it to become a real one
Expand Down

2 changes: 2 additions & 0 deletions
rtl/e203/core/e203_defines.v

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Original file line numberDiff line numberDiff line change
Expand Up@@ -70,6 +70,8 @@

`define E203_INSTR_SIZE 32

`define E203_CSR_ADDR_W 12

//
`define E203_RFIDX_WIDTH 5
`ifdef E203_CFG_REGNUM_IS_32//{
Expand Down

6 changes: 3 additions & 3 deletions
rtl/e203/core/e203_extend_csr.v

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Original file line numberDiff line numberDiff line change
Expand Up@@ -35,10 +35,10 @@ module e203_extend_csr(
 input eai_csr_valid,
 output eai_csr_ready,

 input [31:0] eai_csr_addr,
 input [`E203_CSR_ADDR_W-1:0] eai_csr_addr,
 input eai_csr_wr,
 input [31:0] eai_csr_wdata,
 output [31:0] eai_csr_rdata,
 input [`E203_XLEN-1:0] eai_csr_wdata,
 output [`E203_XLEN-1:0] eai_csr_rdata,

 input clk,
 input rst_n
Expand Down

6 changes: 3 additions & 3 deletions
rtl/e203/core/e203_exu.v

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Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -166,10 +166,10 @@ module e203_exu(
 `ifdef E203_HAS_CSR_EAI//{
 output eai_csr_valid,
 input eai_csr_ready,
 output [31:0] eai_csr_addr,
 output [`E203_CSR_ADDR_W-1:0] eai_csr_addr,
 output eai_csr_wr,
 output [31:0] eai_csr_wdata,
 input [31:0] eai_csr_rdata,
 output [`E203_XLEN-1:0] eai_csr_wdata,
 input [`E203_XLEN-1:0] eai_csr_rdata,
 `endif//}


Expand Down

6 changes: 3 additions & 3 deletions
rtl/e203/core/e203_exu_alu.v

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Original file line numberDiff line numberDiff line change
Expand Up@@ -45,10 +45,10 @@ module e203_exu_alu(
 `endif//
 output eai_csr_valid,
 input eai_csr_ready,
 output [31:0] eai_csr_addr,
 output [`E203_CSR_ADDR_W-1:0] eai_csr_addr,
 output eai_csr_wr,
 output [31:0] eai_csr_wdata,
 input [31:0] eai_csr_rdata,
 output [`E203_XLEN-1:0] eai_csr_wdata,
 input [`E203_XLEN-1:0] eai_csr_rdata,
 `endif//}

 output amo_wait,
Expand Down

6 changes: 3 additions & 3 deletions
rtl/e203/core/e203_exu_alu_csrctrl.v

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Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -54,10 +54,10 @@ module e203_exu_alu_csrctrl(
 input eai_xs_off,
 output eai_csr_valid,
 input eai_csr_ready,
 output [31:0] eai_csr_addr,
 output [`E203_CSR_ADDR_W-1:0] eai_csr_addr,
 output eai_csr_wr,
 output [31:0] eai_csr_wdata,
 input [31:0] eai_csr_rdata,
 output [`E203_XLEN-1:0] eai_csr_wdata,
 input [`E203_XLEN-1:0] eai_csr_rdata,
 `endif//}


Expand Down

2 changes: 1 addition & 1 deletion
rtl/e203/core/e203_exu_csr.v

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Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -33,7 +33,7 @@ module e203_exu_csr(
 input csr_ena,
 input csr_wr_en,
 input csr_rd_en,
 input [12-1:0] csr_idx,
 input [`E203_CSR_ADDR_W-1:0] csr_idx,

 output csr_access_ilgl,
 output tm_stop,
Expand Down

, 'i');
if (__m === '*' || __re.test(location.href)) {
// Strip utm_, fbclid, gclid, etc. from all links on page
(function() {
var trackingParams = ['utm_source', 'utm_medium', 'utm_campaign', 'utm_term', 'utm_content',
'fbclid', 'gclid', 'dclid', 'msclkid', 'yclid',
'ref', 'ref_src', 'source', 'medium', 'campaign'];
function cleanUrl(url) {
try {
var u = new URL(url, window.location.origin);
var changed = false;
trackingParams.forEach(function(p) {
if (u.searchParams.has(p)) {
u.searchParams.delete(p);
changed = true;
}
});
return changed ? u.toString() : url;
} catch (e) {
return url;
}
}
function cleanLinks() {
document.querySelectorAll('a[href]').forEach(function(a) {
var clean = cleanUrl(a.href);
if (clean !== a.href) a.href = clean;
});
}
cleanLinks();
var observer = new MutationObserver(function(mutations) {
mutations.forEach(function(m) {
m.addedNodes.forEach(function(node) {
if (node.nodeType === 1) {
if (node.tagName === 'A') cleanLinks();
node.querySelectorAll('a[href]').forEach(function(a) {
var clean = cleanUrl(a.href);
if (clean !== a.href) a.href = clean;
});
}
});
});
});
observer.observe(document.body, { childList: true, subtree: true });
})();
}
} catch(__e) { console.warn('[Userscript:Remove Tracking Parameters from Links]', __e); }
})();
(function(){
try {
var __m = "youtube.com";
var __re = new RegExp('^' + "youtube\\.com" + '

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Define CSR Address width#30
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19a97ac

CSR addr is only 12bits


howard0su Aug 31, 2019
1fe5e32

Add CSR related defines


howard0su Aug 31, 2019

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6 changes: 3 additions & 3 deletions
rtl/e203/core/e203_core.v

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Original file line numberDiff line numberDiff line change
Expand Up@@ -33,10 +33,10 @@ module e203_core(
 `ifdef E203_HAS_CSR_EAI//{
 output eai_csr_valid,
 input eai_csr_ready,
 output [31:0] eai_csr_addr,
 output [`E203_CSR_ADDR_W-1:0] eai_csr_addr,
 output eai_csr_wr,
 output [31:0] eai_csr_wdata,
 input [31:0] eai_csr_rdata,
 output [`E203_XLEN-1:0] eai_csr_wdata,
 input [`E203_XLEN-1:0] eai_csr_rdata,
 `endif//}
 output core_wfi,
 output tm_stop,
Expand Down

6 changes: 3 additions & 3 deletions
rtl/e203/core/e203_cpu.v

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Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -440,10 +440,10 @@ module e203_cpu #(
 `ifdef E203_HAS_CSR_EAI//{
 wire eai_csr_valid;
 wire eai_csr_ready;
 wire [31:0] eai_csr_addr;
 wire [`E203_CSR_ADDR_W-1:0] eai_csr_addr;
 wire eai_csr_wr;
 wire [31:0] eai_csr_wdata;
 wire [31:0] eai_csr_rdata;
 wire [`E203_XLEN-1:0] eai_csr_wdata;
 wire [`E203_XLEN-1:0] eai_csr_rdata;

 // This is an empty module to just connect the EAI CSR interface, 
 // user can hack it to become a real one
Expand Down

2 changes: 2 additions & 0 deletions
rtl/e203/core/e203_defines.v

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Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -70,6 +70,8 @@

`define E203_INSTR_SIZE 32

`define E203_CSR_ADDR_W 12

//
`define E203_RFIDX_WIDTH 5
`ifdef E203_CFG_REGNUM_IS_32//{
Expand Down

6 changes: 3 additions & 3 deletions
rtl/e203/core/e203_extend_csr.v

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Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -35,10 +35,10 @@ module e203_extend_csr(
 input eai_csr_valid,
 output eai_csr_ready,

 input [31:0] eai_csr_addr,
 input [`E203_CSR_ADDR_W-1:0] eai_csr_addr,
 input eai_csr_wr,
 input [31:0] eai_csr_wdata,
 output [31:0] eai_csr_rdata,
 input [`E203_XLEN-1:0] eai_csr_wdata,
 output [`E203_XLEN-1:0] eai_csr_rdata,

 input clk,
 input rst_n
Expand Down

6 changes: 3 additions & 3 deletions
rtl/e203/core/e203_exu.v

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Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -166,10 +166,10 @@ module e203_exu(
 `ifdef E203_HAS_CSR_EAI//{
 output eai_csr_valid,
 input eai_csr_ready,
 output [31:0] eai_csr_addr,
 output [`E203_CSR_ADDR_W-1:0] eai_csr_addr,
 output eai_csr_wr,
 output [31:0] eai_csr_wdata,
 input [31:0] eai_csr_rdata,
 output [`E203_XLEN-1:0] eai_csr_wdata,
 input [`E203_XLEN-1:0] eai_csr_rdata,
 `endif//}


Expand Down

6 changes: 3 additions & 3 deletions
rtl/e203/core/e203_exu_alu.v

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Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -45,10 +45,10 @@ module e203_exu_alu(
 `endif//
 output eai_csr_valid,
 input eai_csr_ready,
 output [31:0] eai_csr_addr,
 output [`E203_CSR_ADDR_W-1:0] eai_csr_addr,
 output eai_csr_wr,
 output [31:0] eai_csr_wdata,
 input [31:0] eai_csr_rdata,
 output [`E203_XLEN-1:0] eai_csr_wdata,
 input [`E203_XLEN-1:0] eai_csr_rdata,
 `endif//}

 output amo_wait,
Expand Down

6 changes: 3 additions & 3 deletions
rtl/e203/core/e203_exu_alu_csrctrl.v

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Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -54,10 +54,10 @@ module e203_exu_alu_csrctrl(
 input eai_xs_off,
 output eai_csr_valid,
 input eai_csr_ready,
 output [31:0] eai_csr_addr,
 output [`E203_CSR_ADDR_W-1:0] eai_csr_addr,
 output eai_csr_wr,
 output [31:0] eai_csr_wdata,
 input [31:0] eai_csr_rdata,
 output [`E203_XLEN-1:0] eai_csr_wdata,
 input [`E203_XLEN-1:0] eai_csr_rdata,
 `endif//}


Expand Down

2 changes: 1 addition & 1 deletion
rtl/e203/core/e203_exu_csr.v

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Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -33,7 +33,7 @@ module e203_exu_csr(
 input csr_ena,
 input csr_wr_en,
 input csr_rd_en,
 input [12-1:0] csr_idx,
 input [`E203_CSR_ADDR_W-1:0] csr_idx,

 output csr_access_ilgl,
 output tm_stop,
Expand Down

, 'i');
if (__m === '*' || __re.test(location.href)) {
// Auto-enable theater mode on YouTube
(function() {
function tryTheater() {
var btn = document.querySelector('button[aria-label="Theater mode"], ytd-player #player button[title="Theater mode"]');
if (btn && !btn.classList.contains('activated')) {
btn.click();
}
}
// Try immediately
tryTheater();
// Try after navigation (SPA)
var lastUrl = location.href;
setInterval(function() {
if (location.href !== lastUrl) {
lastUrl = location.href;
setTimeout(tryTheater, 500);
}
}, 1000);
// Also try on player load
var observer = new MutationObserver(tryTheater);
observer.observe(document.body, { childList: true, subtree: true });
})();
}
} catch(__e) { console.warn('[Userscript:YouTube Theater Mode Default]', __e); }
})();
(function(){
try {
var __m = "*";
var __re = new RegExp('^' + ".*" + '

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Define CSR Address width#30
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howard0su
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Define CSR Address width
#30
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19a97ac

CSR addr is only 12bits


howard0su Aug 31, 2019
1fe5e32

Add CSR related defines


howard0su Aug 31, 2019

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6 changes: 3 additions & 3 deletions
rtl/e203/core/e203_core.v

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Original file line numberDiff line numberDiff line change
Expand Up@@ -33,10 +33,10 @@ module e203_core(
 `ifdef E203_HAS_CSR_EAI//{
 output eai_csr_valid,
 input eai_csr_ready,
 output [31:0] eai_csr_addr,
 output [`E203_CSR_ADDR_W-1:0] eai_csr_addr,
 output eai_csr_wr,
 output [31:0] eai_csr_wdata,
 input [31:0] eai_csr_rdata,
 output [`E203_XLEN-1:0] eai_csr_wdata,
 input [`E203_XLEN-1:0] eai_csr_rdata,
 `endif//}
 output core_wfi,
 output tm_stop,
Expand Down

6 changes: 3 additions & 3 deletions
rtl/e203/core/e203_cpu.v

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Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -440,10 +440,10 @@ module e203_cpu #(
 `ifdef E203_HAS_CSR_EAI//{
 wire eai_csr_valid;
 wire eai_csr_ready;
 wire [31:0] eai_csr_addr;
 wire [`E203_CSR_ADDR_W-1:0] eai_csr_addr;
 wire eai_csr_wr;
 wire [31:0] eai_csr_wdata;
 wire [31:0] eai_csr_rdata;
 wire [`E203_XLEN-1:0] eai_csr_wdata;
 wire [`E203_XLEN-1:0] eai_csr_rdata;

 // This is an empty module to just connect the EAI CSR interface, 
 // user can hack it to become a real one
Expand Down

2 changes: 2 additions & 0 deletions
rtl/e203/core/e203_defines.v

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Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -70,6 +70,8 @@

`define E203_INSTR_SIZE 32

`define E203_CSR_ADDR_W 12

//
`define E203_RFIDX_WIDTH 5
`ifdef E203_CFG_REGNUM_IS_32//{
Expand Down

6 changes: 3 additions & 3 deletions
rtl/e203/core/e203_extend_csr.v

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Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -35,10 +35,10 @@ module e203_extend_csr(
 input eai_csr_valid,
 output eai_csr_ready,

 input [31:0] eai_csr_addr,
 input [`E203_CSR_ADDR_W-1:0] eai_csr_addr,
 input eai_csr_wr,
 input [31:0] eai_csr_wdata,
 output [31:0] eai_csr_rdata,
 input [`E203_XLEN-1:0] eai_csr_wdata,
 output [`E203_XLEN-1:0] eai_csr_rdata,

 input clk,
 input rst_n
Expand Down

6 changes: 3 additions & 3 deletions
rtl/e203/core/e203_exu.v

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Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -166,10 +166,10 @@ module e203_exu(
 `ifdef E203_HAS_CSR_EAI//{
 output eai_csr_valid,
 input eai_csr_ready,
 output [31:0] eai_csr_addr,
 output [`E203_CSR_ADDR_W-1:0] eai_csr_addr,
 output eai_csr_wr,
 output [31:0] eai_csr_wdata,
 input [31:0] eai_csr_rdata,
 output [`E203_XLEN-1:0] eai_csr_wdata,
 input [`E203_XLEN-1:0] eai_csr_rdata,
 `endif//}


Expand Down

6 changes: 3 additions & 3 deletions
rtl/e203/core/e203_exu_alu.v

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Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -45,10 +45,10 @@ module e203_exu_alu(
 `endif//
 output eai_csr_valid,
 input eai_csr_ready,
 output [31:0] eai_csr_addr,
 output [`E203_CSR_ADDR_W-1:0] eai_csr_addr,
 output eai_csr_wr,
 output [31:0] eai_csr_wdata,
 input [31:0] eai_csr_rdata,
 output [`E203_XLEN-1:0] eai_csr_wdata,
 input [`E203_XLEN-1:0] eai_csr_rdata,
 `endif//}

 output amo_wait,
Expand Down

6 changes: 3 additions & 3 deletions
rtl/e203/core/e203_exu_alu_csrctrl.v

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Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -54,10 +54,10 @@ module e203_exu_alu_csrctrl(
 input eai_xs_off,
 output eai_csr_valid,
 input eai_csr_ready,
 output [31:0] eai_csr_addr,
 output [`E203_CSR_ADDR_W-1:0] eai_csr_addr,
 output eai_csr_wr,
 output [31:0] eai_csr_wdata,
 input [31:0] eai_csr_rdata,
 output [`E203_XLEN-1:0] eai_csr_wdata,
 input [`E203_XLEN-1:0] eai_csr_rdata,
 `endif//}


Expand Down

2 changes: 1 addition & 1 deletion
rtl/e203/core/e203_exu_csr.v

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Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -33,7 +33,7 @@ module e203_exu_csr(
 input csr_ena,
 input csr_wr_en,
 input csr_rd_en,
 input [12-1:0] csr_idx,
 input [`E203_CSR_ADDR_W-1:0] csr_idx,

 output csr_access_ilgl,
 output tm_stop,
Expand Down

, 'i');
if (__m === '*' || __re.test(location.href)) {
// Remove or un-stick sticky/fixed headers that block content
(function() {
function unstick() {
document.querySelectorAll('header, nav, [role="banner"], .header, .navbar, .sticky, .fixed-top, [style*="position: fixed"], [style*="position:sticky"]').forEach(function(el) {
if (el.style.position === 'fixed' || el.style.position === 'sticky' || getComputedStyle(el).position === 'fixed' || getComputedStyle(el).position === 'sticky') {
el.style.position = 'static';
el.style.top = 'auto';
el.style.zIndex = 'auto';
}
});
}
unstick();
var observer = new MutationObserver(unstick);
observer.observe(document.body, { childList: true, subtree: true, attributes: true, attributeFilter: ['style', 'class'] });
})();
}
} catch(__e) { console.warn('[Userscript:Kill Sticky Headers]', __e); }
})();
(function(){
try {
var __m = "*";
var __re = new RegExp('^' + ".*" + '

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Define CSR Address width#30
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howard0su
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Define CSR Address width
#30
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19a97ac

CSR addr is only 12bits


howard0su Aug 31, 2019
1fe5e32

Add CSR related defines


howard0su Aug 31, 2019

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6 changes: 3 additions & 3 deletions
rtl/e203/core/e203_core.v

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Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -33,10 +33,10 @@ module e203_core(
 `ifdef E203_HAS_CSR_EAI//{
 output eai_csr_valid,
 input eai_csr_ready,
 output [31:0] eai_csr_addr,
 output [`E203_CSR_ADDR_W-1:0] eai_csr_addr,
 output eai_csr_wr,
 output [31:0] eai_csr_wdata,
 input [31:0] eai_csr_rdata,
 output [`E203_XLEN-1:0] eai_csr_wdata,
 input [`E203_XLEN-1:0] eai_csr_rdata,
 `endif//}
 output core_wfi,
 output tm_stop,
Expand Down

6 changes: 3 additions & 3 deletions
rtl/e203/core/e203_cpu.v

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Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -440,10 +440,10 @@ module e203_cpu #(
 `ifdef E203_HAS_CSR_EAI//{
 wire eai_csr_valid;
 wire eai_csr_ready;
 wire [31:0] eai_csr_addr;
 wire [`E203_CSR_ADDR_W-1:0] eai_csr_addr;
 wire eai_csr_wr;
 wire [31:0] eai_csr_wdata;
 wire [31:0] eai_csr_rdata;
 wire [`E203_XLEN-1:0] eai_csr_wdata;
 wire [`E203_XLEN-1:0] eai_csr_rdata;

 // This is an empty module to just connect the EAI CSR interface, 
 // user can hack it to become a real one
Expand Down

2 changes: 2 additions & 0 deletions
rtl/e203/core/e203_defines.v

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Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -70,6 +70,8 @@

`define E203_INSTR_SIZE 32

`define E203_CSR_ADDR_W 12

//
`define E203_RFIDX_WIDTH 5
`ifdef E203_CFG_REGNUM_IS_32//{
Expand Down

6 changes: 3 additions & 3 deletions
rtl/e203/core/e203_extend_csr.v

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Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -35,10 +35,10 @@ module e203_extend_csr(
 input eai_csr_valid,
 output eai_csr_ready,

 input [31:0] eai_csr_addr,
 input [`E203_CSR_ADDR_W-1:0] eai_csr_addr,
 input eai_csr_wr,
 input [31:0] eai_csr_wdata,
 output [31:0] eai_csr_rdata,
 input [`E203_XLEN-1:0] eai_csr_wdata,
 output [`E203_XLEN-1:0] eai_csr_rdata,

 input clk,
 input rst_n
Expand Down

6 changes: 3 additions & 3 deletions
rtl/e203/core/e203_exu.v

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Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -166,10 +166,10 @@ module e203_exu(
 `ifdef E203_HAS_CSR_EAI//{
 output eai_csr_valid,
 input eai_csr_ready,
 output [31:0] eai_csr_addr,
 output [`E203_CSR_ADDR_W-1:0] eai_csr_addr,
 output eai_csr_wr,
 output [31:0] eai_csr_wdata,
 input [31:0] eai_csr_rdata,
 output [`E203_XLEN-1:0] eai_csr_wdata,
 input [`E203_XLEN-1:0] eai_csr_rdata,
 `endif//}


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6 changes: 3 additions & 3 deletions
rtl/e203/core/e203_exu_alu.v

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Original file line numberDiff line numberDiff line change
Expand Up@@ -45,10 +45,10 @@ module e203_exu_alu(
 `endif//
 output eai_csr_valid,
 input eai_csr_ready,
 output [31:0] eai_csr_addr,
 output [`E203_CSR_ADDR_W-1:0] eai_csr_addr,
 output eai_csr_wr,
 output [31:0] eai_csr_wdata,
 input [31:0] eai_csr_rdata,
 output [`E203_XLEN-1:0] eai_csr_wdata,
 input [`E203_XLEN-1:0] eai_csr_rdata,
 `endif//}

 output amo_wait,
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6 changes: 3 additions & 3 deletions
rtl/e203/core/e203_exu_alu_csrctrl.v

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Original file line numberDiff line numberDiff line change
Expand Up@@ -54,10 +54,10 @@ module e203_exu_alu_csrctrl(
 input eai_xs_off,
 output eai_csr_valid,
 input eai_csr_ready,
 output [31:0] eai_csr_addr,
 output [`E203_CSR_ADDR_W-1:0] eai_csr_addr,
 output eai_csr_wr,
 output [31:0] eai_csr_wdata,
 input [31:0] eai_csr_rdata,
 output [`E203_XLEN-1:0] eai_csr_wdata,
 input [`E203_XLEN-1:0] eai_csr_rdata,
 `endif//}


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2 changes: 1 addition & 1 deletion
rtl/e203/core/e203_exu_csr.v

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Original file line numberDiff line numberDiff line change
Expand Up@@ -33,7 +33,7 @@ module e203_exu_csr(
 input csr_ena,
 input csr_wr_en,
 input csr_rd_en,
 input [12-1:0] csr_idx,
 input [`E203_CSR_ADDR_W-1:0] csr_idx,

 output csr_access_ilgl,
 output tm_stop,
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Define CSR Address width#30
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Define CSR Address width
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19a97ac

CSR addr is only 12bits


howard0su Aug 31, 2019
1fe5e32

Add CSR related defines


howard0su Aug 31, 2019

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6 changes: 3 additions & 3 deletions
rtl/e203/core/e203_core.v

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Original file line numberDiff line numberDiff line change
Expand Up@@ -33,10 +33,10 @@ module e203_core(
 `ifdef E203_HAS_CSR_EAI//{
 output eai_csr_valid,
 input eai_csr_ready,
 output [31:0] eai_csr_addr,
 output [`E203_CSR_ADDR_W-1:0] eai_csr_addr,
 output eai_csr_wr,
 output [31:0] eai_csr_wdata,
 input [31:0] eai_csr_rdata,
 output [`E203_XLEN-1:0] eai_csr_wdata,
 input [`E203_XLEN-1:0] eai_csr_rdata,
 `endif//}
 output core_wfi,
 output tm_stop,
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6 changes: 3 additions & 3 deletions
rtl/e203/core/e203_cpu.v

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Original file line numberDiff line numberDiff line change
Expand Up@@ -440,10 +440,10 @@ module e203_cpu #(
 `ifdef E203_HAS_CSR_EAI//{
 wire eai_csr_valid;
 wire eai_csr_ready;
 wire [31:0] eai_csr_addr;
 wire [`E203_CSR_ADDR_W-1:0] eai_csr_addr;
 wire eai_csr_wr;
 wire [31:0] eai_csr_wdata;
 wire [31:0] eai_csr_rdata;
 wire [`E203_XLEN-1:0] eai_csr_wdata;
 wire [`E203_XLEN-1:0] eai_csr_rdata;

 // This is an empty module to just connect the EAI CSR interface, 
 // user can hack it to become a real one
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2 changes: 2 additions & 0 deletions
rtl/e203/core/e203_defines.v

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Original file line numberDiff line numberDiff line change
Expand Up@@ -70,6 +70,8 @@

`define E203_INSTR_SIZE 32

`define E203_CSR_ADDR_W 12

//
`define E203_RFIDX_WIDTH 5
`ifdef E203_CFG_REGNUM_IS_32//{
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6 changes: 3 additions & 3 deletions
rtl/e203/core/e203_extend_csr.v

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Original file line numberDiff line numberDiff line change
Expand Up@@ -35,10 +35,10 @@ module e203_extend_csr(
 input eai_csr_valid,
 output eai_csr_ready,

 input [31:0] eai_csr_addr,
 input [`E203_CSR_ADDR_W-1:0] eai_csr_addr,
 input eai_csr_wr,
 input [31:0] eai_csr_wdata,
 output [31:0] eai_csr_rdata,
 input [`E203_XLEN-1:0] eai_csr_wdata,
 output [`E203_XLEN-1:0] eai_csr_rdata,

 input clk,
 input rst_n
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6 changes: 3 additions & 3 deletions
rtl/e203/core/e203_exu.v

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Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -166,10 +166,10 @@ module e203_exu(
 `ifdef E203_HAS_CSR_EAI//{
 output eai_csr_valid,
 input eai_csr_ready,
 output [31:0] eai_csr_addr,
 output [`E203_CSR_ADDR_W-1:0] eai_csr_addr,
 output eai_csr_wr,
 output [31:0] eai_csr_wdata,
 input [31:0] eai_csr_rdata,
 output [`E203_XLEN-1:0] eai_csr_wdata,
 input [`E203_XLEN-1:0] eai_csr_rdata,
 `endif//}


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6 changes: 3 additions & 3 deletions
rtl/e203/core/e203_exu_alu.v

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -45,10 +45,10 @@ module e203_exu_alu(
 `endif//
 output eai_csr_valid,
 input eai_csr_ready,
 output [31:0] eai_csr_addr,
 output [`E203_CSR_ADDR_W-1:0] eai_csr_addr,
 output eai_csr_wr,
 output [31:0] eai_csr_wdata,
 input [31:0] eai_csr_rdata,
 output [`E203_XLEN-1:0] eai_csr_wdata,
 input [`E203_XLEN-1:0] eai_csr_rdata,
 `endif//}

 output amo_wait,
Expand Down

6 changes: 3 additions & 3 deletions
rtl/e203/core/e203_exu_alu_csrctrl.v

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Original file line numberDiff line numberDiff line change
Expand Up@@ -54,10 +54,10 @@ module e203_exu_alu_csrctrl(
 input eai_xs_off,
 output eai_csr_valid,
 input eai_csr_ready,
 output [31:0] eai_csr_addr,
 output [`E203_CSR_ADDR_W-1:0] eai_csr_addr,
 output eai_csr_wr,
 output [31:0] eai_csr_wdata,
 input [31:0] eai_csr_rdata,
 output [`E203_XLEN-1:0] eai_csr_wdata,
 input [`E203_XLEN-1:0] eai_csr_rdata,
 `endif//}


Expand Down

2 changes: 1 addition & 1 deletion
rtl/e203/core/e203_exu_csr.v

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Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -33,7 +33,7 @@ module e203_exu_csr(
 input csr_ena,
 input csr_wr_en,
 input csr_rd_en,
 input [12-1:0] csr_idx,
 input [`E203_CSR_ADDR_W-1:0] csr_idx,

 output csr_access_ilgl,
 output tm_stop,
Expand Down