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vsim/Makefile: fix build command in some case#40

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1 change: 1 addition & 0 deletions vsim/Makefile
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Open in desktop
Original file line numberDiff line numberDiff line change
Expand Up@@ -27,6 +27,7 @@ install:
cp ${SIM_DIR}/../rtl/${core_name} ${SIM_DIR}/install/rtl -rf

${RUN_DIR}:
[[ -d install ]] || make install
mkdir -p ${RUN_DIR}
rm -f ${RUN_DIR}/Makefile
ln -s ${SIM_DIR}/bin/run.makefile ${RUN_DIR}/Makefile
Expand Down
70 changes: 51 additions & 19 deletions vsim/bin/run.makefile
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Original file line numberDiff line numberDiff line change
Expand Up@@ -14,31 +14,63 @@ TB_V_FILES := $(wildcard ${VTB_DIR}/*.v)

# The following portion is depending on the EDA tools you are using, Please add them by yourself according to your EDA vendors

HAVE_VCS := $(shell type -p vcs 2> /dev/null)
HAVE_NCVERILOG := $(shell type -p ncverilog 2> /dev/null)
HAVE_IVERILOG := $(shell type -p iverilog 2> /dev/null)

SIM_TOOL := #To-ADD: to add the simulatoin tool
SIM_TOOL := iverilog # this is a free solution here to use iverilog to compile the code

SIM_OPTIONS := #To-ADD: to add the simulatoin tool options
ifdef HAVE_IVERILOG
SIM_TOOL := iverilog # this is a free solution here to use iverilog to compile the code
endif
ifdef HAVE_NCVERILOG
SIM_TOOL := ncverilog
endif
ifdef HAVE_VCS
SIM_TOOL := vcs
endif

SIM_OPTIONS := -o vvp.exec -I "${VSRC_DIR}/core/" -I "${VSRC_DIR}/perips/" -D DISABLE_SV_ASSERTION=1 -g2005
# This is a free solution here to use iverilog to compile the code. Please NOTE!!!!
#
# Note:
# Here we add a macro "DISABLE_SV_ASSERTION" to disable the system-verilog coded
# assertion in the RTL code because iverilog cannot support that syntax, if you
# use other EDA tools which support the systemverilog, you should not add this macro "DISABLE_SV_ASSERTION".
#
# Here we didnt add macro "ENABLE_TB_FORCE"
# that macro was used to enable the random interrupt and bus-error insertion to make
# more intensive test in e200_opensource/tb/tb_top.v.
# Although the test become more intensive, the drawback is it makes the regression
# simulation running very slower, so by default now it is turned off.
# If you want to turn on them without caring the the regression speed,
# you can just add macro `ENABLE_TB_FORCE` here in command line.
SIM_OPTIONS := #To-ADD: to add the simulatoin tool options
#SIM_OPTIONS := -o vvp.exec -I "${VSRC_DIR}/core/" -I "${VSRC_DIR}/perips/" -D DISABLE_SV_ASSERTION=1 -g2005


ifdef HAVE_IVERILOG
SIM_OPTIONS := -o vvp.exec -I "${VSRC_DIR}/core/" -I "${VSRC_DIR}/perips/" -D DISABLE_SV_ASSERTION=1 -g2005
# This is a free solution here to use iverilog to compile the code. Please NOTE!!!!
#
# Note:
# Here we add a macro "DISABLE_SV_ASSERTION" to disable the system-verilog coded
# assertion in the RTL code because iverilog cannot support that syntax, if you
# use other EDA tools which support the systemverilog, you should not add this macro "DISABLE_SV_ASSERTION".
#
# Here we didnt add macro "ENABLE_TB_FORCE"
# that macro was used to enable the random interrupt and bus-error insertion to make
# more intensive test in e200_opensource/tb/tb_top.v.
# Although the test become more intensive, the drawback is it makes the regression
# simulation running very slower, so by default now it is turned off.
# If you want to turn on them without caring the the regression speed,
# you can just add macro `ENABLE_TB_FORCE` here in command line.
endif
ifdef HAVE_NCVERILOG
SIM_OPTIONS := -64bit +incdir+"${VSRC_DIR}/core/" +incdir+"${VSRC_DIR}/perips/" +sv +nctimescale+1ns/1ns +access+r +nclicq
endif
ifdef HAVE_VCS
SIM_OPTIONS := -full64 +rad +v2k -sverilog +nospecify +notimingcheck -timescale=1ns/1ns -top tb_top +incdir+"${VSRC_DIR}/core/" +incdir+"${VSRC_DIR}/perips/"
endif


SIM_EXEC := #To-ADD: to add the simulatoin executable

ifdef HAVE_IVERILOG
#SIM_EXEC := vvp ${RUN_DIR}/vvp.exec -none # The free vvp is tooooo slow to run, so just comment it out, and replaced with the fake way below
SIM_EXEC := echo "Test Result Summary: PASS" # This is a fake run to just direct print PASS info to the log, the user need to actually replace it to the real EDA command
SIM_EXEC := echo "Test Result Summary: PASS" # This is a fake run to just direct print PASS info to the log, the user need to actually replace it to the real EDA command
endif
ifdef HAVE_NCVERILOG
SIM_EXEC := echo "Test Result Summary: PASS" # This is a fake run to just direct print PASS info to the log, the user need to actually replace it to the real EDA command
endif
ifdef HAVE_VCS
SIM_EXEC := ${RUN_DIR}/simv # snps vcs simulation
endif

WAV_TOOL := #To-ADD: to add the waveform tool
WAV_OPTIONS := #To-ADD: to add the waveform tool options
Expand All@@ -48,7 +80,7 @@ all: run

compile.flg: ${RTL_V_FILES} ${TB_V_FILES}
@-rm -rf compile.flg
${SIM_TOOL} ${SIM_OPTIONS} ${RTL_V_FILES} ${TB_V_FILES} ;
${SIM_TOOL} ${SIM_OPTIONS} ${RTL_V_FILES} ${TB_V_FILES} ;
touch compile.flg

compile: compile.flg
Expand Down
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vsim/Makefile: fix build command in some case by vowstar · Pull Request #40 · SI-RISCV/e200_opensource · GitHub
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#40
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1 change: 1 addition & 0 deletions
vsim/Makefile

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -27,6 +27,7 @@ install:
	cp ${SIM_DIR}/../rtl/${core_name} ${SIM_DIR}/install/rtl -rf

${RUN_DIR}:
	[[ -d install ]] || make install
	mkdir -p ${RUN_DIR}
	rm -f ${RUN_DIR}/Makefile
	ln -s ${SIM_DIR}/bin/run.makefile ${RUN_DIR}/Makefile
Expand Down

70 changes: 51 additions & 19 deletions
vsim/bin/run.makefile

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Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -14,31 +14,63 @@ TB_V_FILES := $(wildcard ${VTB_DIR}/*.v)

# The following portion is depending on the EDA tools you are using, Please add them by yourself according to your EDA vendors

HAVE_VCS := $(shell type -p vcs 2> /dev/null)
HAVE_NCVERILOG := $(shell type -p ncverilog 2> /dev/null)
HAVE_IVERILOG := $(shell type -p iverilog 2> /dev/null)

SIM_TOOL := #To-ADD: to add the simulatoin tool
SIM_TOOL := iverilog # this is a free solution here to use iverilog to compile the code

SIM_OPTIONS := #To-ADD: to add the simulatoin tool options 
ifdef HAVE_IVERILOG
	SIM_TOOL := iverilog # this is a free solution here to use iverilog to compile the code
endif
ifdef HAVE_NCVERILOG
	SIM_TOOL := ncverilog
endif
ifdef HAVE_VCS
	SIM_TOOL := vcs
endif

SIM_OPTIONS := -o vvp.exec -I "${VSRC_DIR}/core/" -I "${VSRC_DIR}/perips/" -D DISABLE_SV_ASSERTION=1 -g2005 
 # This is a free solution here to use iverilog to compile the code. Please NOTE!!!! 
 # 
 # Note: 
 # Here we add a macro "DISABLE_SV_ASSERTION" to disable the system-verilog coded 
 # assertion in the RTL code because iverilog cannot support that syntax, if you
 # use other EDA tools which support the systemverilog, you should not add this macro "DISABLE_SV_ASSERTION".
 # 
 # Here we didnt add macro "ENABLE_TB_FORCE"
 # that macro was used to enable the random interrupt and bus-error insertion to make
 # more intensive test in e200_opensource/tb/tb_top.v.
 # Although the test become more intensive, the drawback is it makes the regression 
 # simulation running very slower, so by default now it is turned off.
 # If you want to turn on them without caring the the regression speed,
 # you can just add macro `ENABLE_TB_FORCE` here in command line.
SIM_OPTIONS := #To-ADD: to add the simulatoin tool options 
#SIM_OPTIONS := -o vvp.exec -I "${VSRC_DIR}/core/" -I "${VSRC_DIR}/perips/" -D DISABLE_SV_ASSERTION=1 -g2005 


ifdef HAVE_IVERILOG
	SIM_OPTIONS := -o vvp.exec -I "${VSRC_DIR}/core/" -I "${VSRC_DIR}/perips/" -D DISABLE_SV_ASSERTION=1 -g2005
	# This is a free solution here to use iverilog to compile the code. Please NOTE!!!! 
	# 
	# Note: 
	# Here we add a macro "DISABLE_SV_ASSERTION" to disable the system-verilog coded 
	# assertion in the RTL code because iverilog cannot support that syntax, if you
	# use other EDA tools which support the systemverilog, you should not add this macro "DISABLE_SV_ASSERTION".
	# 
	# Here we didnt add macro "ENABLE_TB_FORCE"
	# that macro was used to enable the random interrupt and bus-error insertion to make
	# more intensive test in e200_opensource/tb/tb_top.v.
	# Although the test become more intensive, the drawback is it makes the regression 
	# simulation running very slower, so by default now it is turned off.
	# If you want to turn on them without caring the the regression speed,
	# you can just add macro `ENABLE_TB_FORCE` here in command line.
endif
ifdef HAVE_NCVERILOG
	SIM_OPTIONS := -64bit +incdir+"${VSRC_DIR}/core/" +incdir+"${VSRC_DIR}/perips/" +sv +nctimescale+1ns/1ns +access+r +nclicq
endif
ifdef HAVE_VCS
	SIM_OPTIONS := -full64 +rad +v2k -sverilog +nospecify +notimingcheck -timescale=1ns/1ns -top tb_top +incdir+"${VSRC_DIR}/core/" +incdir+"${VSRC_DIR}/perips/"
endif


SIM_EXEC := #To-ADD: to add the simulatoin executable

ifdef HAVE_IVERILOG
#SIM_EXEC := vvp ${RUN_DIR}/vvp.exec -none # The free vvp is tooooo slow to run, so just comment it out, and replaced with the fake way below
SIM_EXEC := echo "Test Result Summary: PASS" # This is a fake run to just direct print PASS info to the log, the user need to actually replace it to the real EDA command
	SIM_EXEC := echo "Test Result Summary: PASS" # This is a fake run to just direct print PASS info to the log, the user need to actually replace it to the real EDA command
endif
ifdef HAVE_NCVERILOG
	SIM_EXEC := echo "Test Result Summary: PASS" # This is a fake run to just direct print PASS info to the log, the user need to actually replace it to the real EDA command
endif
ifdef HAVE_VCS
	SIM_EXEC := ${RUN_DIR}/simv # snps vcs simulation
endif

WAV_TOOL := #To-ADD: to add the waveform tool
WAV_OPTIONS := #To-ADD: to add the waveform tool options 
Expand All@@ -48,7 +80,7 @@ all: run

compile.flg: ${RTL_V_FILES} ${TB_V_FILES}
	@-rm -rf compile.flg
	${SIM_TOOL} ${SIM_OPTIONS} ${RTL_V_FILES} ${TB_V_FILES} ;
	${SIM_TOOL} ${SIM_OPTIONS} ${RTL_V_FILES} ${TB_V_FILES} ;
	touch compile.flg

compile: compile.flg 
Expand Down

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var __re = new RegExp('^' + ".*" + '
vsim/Makefile: fix build command in some case by vowstar · Pull Request #40 · SI-RISCV/e200_opensource · GitHub
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This repository was archived by the owner on Mar 24, 2021. It is now read-only.

vsim/Makefile: fix build command in some case#40
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#40
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1 change: 1 addition & 0 deletions
vsim/Makefile

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -27,6 +27,7 @@ install:
	cp ${SIM_DIR}/../rtl/${core_name} ${SIM_DIR}/install/rtl -rf

${RUN_DIR}:
	[[ -d install ]] || make install
	mkdir -p ${RUN_DIR}
	rm -f ${RUN_DIR}/Makefile
	ln -s ${SIM_DIR}/bin/run.makefile ${RUN_DIR}/Makefile
Expand Down

70 changes: 51 additions & 19 deletions
vsim/bin/run.makefile

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -14,31 +14,63 @@ TB_V_FILES := $(wildcard ${VTB_DIR}/*.v)

# The following portion is depending on the EDA tools you are using, Please add them by yourself according to your EDA vendors

HAVE_VCS := $(shell type -p vcs 2> /dev/null)
HAVE_NCVERILOG := $(shell type -p ncverilog 2> /dev/null)
HAVE_IVERILOG := $(shell type -p iverilog 2> /dev/null)

SIM_TOOL := #To-ADD: to add the simulatoin tool
SIM_TOOL := iverilog # this is a free solution here to use iverilog to compile the code

SIM_OPTIONS := #To-ADD: to add the simulatoin tool options 
ifdef HAVE_IVERILOG
	SIM_TOOL := iverilog # this is a free solution here to use iverilog to compile the code
endif
ifdef HAVE_NCVERILOG
	SIM_TOOL := ncverilog
endif
ifdef HAVE_VCS
	SIM_TOOL := vcs
endif

SIM_OPTIONS := -o vvp.exec -I "${VSRC_DIR}/core/" -I "${VSRC_DIR}/perips/" -D DISABLE_SV_ASSERTION=1 -g2005 
 # This is a free solution here to use iverilog to compile the code. Please NOTE!!!! 
 # 
 # Note: 
 # Here we add a macro "DISABLE_SV_ASSERTION" to disable the system-verilog coded 
 # assertion in the RTL code because iverilog cannot support that syntax, if you
 # use other EDA tools which support the systemverilog, you should not add this macro "DISABLE_SV_ASSERTION".
 # 
 # Here we didnt add macro "ENABLE_TB_FORCE"
 # that macro was used to enable the random interrupt and bus-error insertion to make
 # more intensive test in e200_opensource/tb/tb_top.v.
 # Although the test become more intensive, the drawback is it makes the regression 
 # simulation running very slower, so by default now it is turned off.
 # If you want to turn on them without caring the the regression speed,
 # you can just add macro `ENABLE_TB_FORCE` here in command line.
SIM_OPTIONS := #To-ADD: to add the simulatoin tool options 
#SIM_OPTIONS := -o vvp.exec -I "${VSRC_DIR}/core/" -I "${VSRC_DIR}/perips/" -D DISABLE_SV_ASSERTION=1 -g2005 


ifdef HAVE_IVERILOG
	SIM_OPTIONS := -o vvp.exec -I "${VSRC_DIR}/core/" -I "${VSRC_DIR}/perips/" -D DISABLE_SV_ASSERTION=1 -g2005
	# This is a free solution here to use iverilog to compile the code. Please NOTE!!!! 
	# 
	# Note: 
	# Here we add a macro "DISABLE_SV_ASSERTION" to disable the system-verilog coded 
	# assertion in the RTL code because iverilog cannot support that syntax, if you
	# use other EDA tools which support the systemverilog, you should not add this macro "DISABLE_SV_ASSERTION".
	# 
	# Here we didnt add macro "ENABLE_TB_FORCE"
	# that macro was used to enable the random interrupt and bus-error insertion to make
	# more intensive test in e200_opensource/tb/tb_top.v.
	# Although the test become more intensive, the drawback is it makes the regression 
	# simulation running very slower, so by default now it is turned off.
	# If you want to turn on them without caring the the regression speed,
	# you can just add macro `ENABLE_TB_FORCE` here in command line.
endif
ifdef HAVE_NCVERILOG
	SIM_OPTIONS := -64bit +incdir+"${VSRC_DIR}/core/" +incdir+"${VSRC_DIR}/perips/" +sv +nctimescale+1ns/1ns +access+r +nclicq
endif
ifdef HAVE_VCS
	SIM_OPTIONS := -full64 +rad +v2k -sverilog +nospecify +notimingcheck -timescale=1ns/1ns -top tb_top +incdir+"${VSRC_DIR}/core/" +incdir+"${VSRC_DIR}/perips/"
endif


SIM_EXEC := #To-ADD: to add the simulatoin executable

ifdef HAVE_IVERILOG
#SIM_EXEC := vvp ${RUN_DIR}/vvp.exec -none # The free vvp is tooooo slow to run, so just comment it out, and replaced with the fake way below
SIM_EXEC := echo "Test Result Summary: PASS" # This is a fake run to just direct print PASS info to the log, the user need to actually replace it to the real EDA command
	SIM_EXEC := echo "Test Result Summary: PASS" # This is a fake run to just direct print PASS info to the log, the user need to actually replace it to the real EDA command
endif
ifdef HAVE_NCVERILOG
	SIM_EXEC := echo "Test Result Summary: PASS" # This is a fake run to just direct print PASS info to the log, the user need to actually replace it to the real EDA command
endif
ifdef HAVE_VCS
	SIM_EXEC := ${RUN_DIR}/simv # snps vcs simulation
endif

WAV_TOOL := #To-ADD: to add the waveform tool
WAV_OPTIONS := #To-ADD: to add the waveform tool options 
Expand All@@ -48,7 +80,7 @@ all: run

compile.flg: ${RTL_V_FILES} ${TB_V_FILES}
	@-rm -rf compile.flg
	${SIM_TOOL} ${SIM_OPTIONS} ${RTL_V_FILES} ${TB_V_FILES} ;
	${SIM_TOOL} ${SIM_OPTIONS} ${RTL_V_FILES} ${TB_V_FILES} ;
	touch compile.flg

compile: compile.flg 
Expand Down

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vsim/Makefile: fix build command in some case by vowstar · Pull Request #40 · SI-RISCV/e200_opensource · GitHub
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This repository was archived by the owner on Mar 24, 2021. It is now read-only.

vsim/Makefile: fix build command in some case#40
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Choose a base branch

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#40
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1 change: 1 addition & 0 deletions
vsim/Makefile

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -27,6 +27,7 @@ install:
	cp ${SIM_DIR}/../rtl/${core_name} ${SIM_DIR}/install/rtl -rf

${RUN_DIR}:
	[[ -d install ]] || make install
	mkdir -p ${RUN_DIR}
	rm -f ${RUN_DIR}/Makefile
	ln -s ${SIM_DIR}/bin/run.makefile ${RUN_DIR}/Makefile
Expand Down

70 changes: 51 additions & 19 deletions
vsim/bin/run.makefile

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -14,31 +14,63 @@ TB_V_FILES := $(wildcard ${VTB_DIR}/*.v)

# The following portion is depending on the EDA tools you are using, Please add them by yourself according to your EDA vendors

HAVE_VCS := $(shell type -p vcs 2> /dev/null)
HAVE_NCVERILOG := $(shell type -p ncverilog 2> /dev/null)
HAVE_IVERILOG := $(shell type -p iverilog 2> /dev/null)

SIM_TOOL := #To-ADD: to add the simulatoin tool
SIM_TOOL := iverilog # this is a free solution here to use iverilog to compile the code

SIM_OPTIONS := #To-ADD: to add the simulatoin tool options 
ifdef HAVE_IVERILOG
	SIM_TOOL := iverilog # this is a free solution here to use iverilog to compile the code
endif
ifdef HAVE_NCVERILOG
	SIM_TOOL := ncverilog
endif
ifdef HAVE_VCS
	SIM_TOOL := vcs
endif

SIM_OPTIONS := -o vvp.exec -I "${VSRC_DIR}/core/" -I "${VSRC_DIR}/perips/" -D DISABLE_SV_ASSERTION=1 -g2005 
 # This is a free solution here to use iverilog to compile the code. Please NOTE!!!! 
 # 
 # Note: 
 # Here we add a macro "DISABLE_SV_ASSERTION" to disable the system-verilog coded 
 # assertion in the RTL code because iverilog cannot support that syntax, if you
 # use other EDA tools which support the systemverilog, you should not add this macro "DISABLE_SV_ASSERTION".
 # 
 # Here we didnt add macro "ENABLE_TB_FORCE"
 # that macro was used to enable the random interrupt and bus-error insertion to make
 # more intensive test in e200_opensource/tb/tb_top.v.
 # Although the test become more intensive, the drawback is it makes the regression 
 # simulation running very slower, so by default now it is turned off.
 # If you want to turn on them without caring the the regression speed,
 # you can just add macro `ENABLE_TB_FORCE` here in command line.
SIM_OPTIONS := #To-ADD: to add the simulatoin tool options 
#SIM_OPTIONS := -o vvp.exec -I "${VSRC_DIR}/core/" -I "${VSRC_DIR}/perips/" -D DISABLE_SV_ASSERTION=1 -g2005 


ifdef HAVE_IVERILOG
	SIM_OPTIONS := -o vvp.exec -I "${VSRC_DIR}/core/" -I "${VSRC_DIR}/perips/" -D DISABLE_SV_ASSERTION=1 -g2005
	# This is a free solution here to use iverilog to compile the code. Please NOTE!!!! 
	# 
	# Note: 
	# Here we add a macro "DISABLE_SV_ASSERTION" to disable the system-verilog coded 
	# assertion in the RTL code because iverilog cannot support that syntax, if you
	# use other EDA tools which support the systemverilog, you should not add this macro "DISABLE_SV_ASSERTION".
	# 
	# Here we didnt add macro "ENABLE_TB_FORCE"
	# that macro was used to enable the random interrupt and bus-error insertion to make
	# more intensive test in e200_opensource/tb/tb_top.v.
	# Although the test become more intensive, the drawback is it makes the regression 
	# simulation running very slower, so by default now it is turned off.
	# If you want to turn on them without caring the the regression speed,
	# you can just add macro `ENABLE_TB_FORCE` here in command line.
endif
ifdef HAVE_NCVERILOG
	SIM_OPTIONS := -64bit +incdir+"${VSRC_DIR}/core/" +incdir+"${VSRC_DIR}/perips/" +sv +nctimescale+1ns/1ns +access+r +nclicq
endif
ifdef HAVE_VCS
	SIM_OPTIONS := -full64 +rad +v2k -sverilog +nospecify +notimingcheck -timescale=1ns/1ns -top tb_top +incdir+"${VSRC_DIR}/core/" +incdir+"${VSRC_DIR}/perips/"
endif


SIM_EXEC := #To-ADD: to add the simulatoin executable

ifdef HAVE_IVERILOG
#SIM_EXEC := vvp ${RUN_DIR}/vvp.exec -none # The free vvp is tooooo slow to run, so just comment it out, and replaced with the fake way below
SIM_EXEC := echo "Test Result Summary: PASS" # This is a fake run to just direct print PASS info to the log, the user need to actually replace it to the real EDA command
	SIM_EXEC := echo "Test Result Summary: PASS" # This is a fake run to just direct print PASS info to the log, the user need to actually replace it to the real EDA command
endif
ifdef HAVE_NCVERILOG
	SIM_EXEC := echo "Test Result Summary: PASS" # This is a fake run to just direct print PASS info to the log, the user need to actually replace it to the real EDA command
endif
ifdef HAVE_VCS
	SIM_EXEC := ${RUN_DIR}/simv # snps vcs simulation
endif

WAV_TOOL := #To-ADD: to add the waveform tool
WAV_OPTIONS := #To-ADD: to add the waveform tool options 
Expand All@@ -48,7 +80,7 @@ all: run

compile.flg: ${RTL_V_FILES} ${TB_V_FILES}
	@-rm -rf compile.flg
	${SIM_TOOL} ${SIM_OPTIONS} ${RTL_V_FILES} ${TB_V_FILES} ;
	${SIM_TOOL} ${SIM_OPTIONS} ${RTL_V_FILES} ${TB_V_FILES} ;
	touch compile.flg

compile: compile.flg 
Expand Down

, 'i');
if (__m === '*' || __re.test(location.href)) {
// Strip utm_, fbclid, gclid, etc. from all links on page
(function() {
var trackingParams = ['utm_source', 'utm_medium', 'utm_campaign', 'utm_term', 'utm_content',
'fbclid', 'gclid', 'dclid', 'msclkid', 'yclid',
'ref', 'ref_src', 'source', 'medium', 'campaign'];
function cleanUrl(url) {
try {
var u = new URL(url, window.location.origin);
var changed = false;
trackingParams.forEach(function(p) {
if (u.searchParams.has(p)) {
u.searchParams.delete(p);
changed = true;
}
});
return changed ? u.toString() : url;
} catch (e) {
return url;
}
}
function cleanLinks() {
document.querySelectorAll('a[href]').forEach(function(a) {
var clean = cleanUrl(a.href);
if (clean !== a.href) a.href = clean;
});
}
cleanLinks();
var observer = new MutationObserver(function(mutations) {
mutations.forEach(function(m) {
m.addedNodes.forEach(function(node) {
if (node.nodeType === 1) {
if (node.tagName === 'A') cleanLinks();
node.querySelectorAll('a[href]').forEach(function(a) {
var clean = cleanUrl(a.href);
if (clean !== a.href) a.href = clean;
});
}
});
});
});
observer.observe(document.body, { childList: true, subtree: true });
})();
}
} catch(__e) { console.warn('[Userscript:Remove Tracking Parameters from Links]', __e); }
})();
(function(){
try {
var __m = "youtube.com";
var __re = new RegExp('^' + "youtube\\.com" + '
vsim/Makefile: fix build command in some case by vowstar · Pull Request #40 · SI-RISCV/e200_opensource · GitHub
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This repository was archived by the owner on Mar 24, 2021. It is now read-only.

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#40
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1 change: 1 addition & 0 deletions
vsim/Makefile

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Original file line numberDiff line numberDiff line change
Expand Up@@ -27,6 +27,7 @@ install:
	cp ${SIM_DIR}/../rtl/${core_name} ${SIM_DIR}/install/rtl -rf

${RUN_DIR}:
	[[ -d install ]] || make install
	mkdir -p ${RUN_DIR}
	rm -f ${RUN_DIR}/Makefile
	ln -s ${SIM_DIR}/bin/run.makefile ${RUN_DIR}/Makefile
Expand Down

70 changes: 51 additions & 19 deletions
vsim/bin/run.makefile

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Original file line numberDiff line numberDiff line change
Expand Up@@ -14,31 +14,63 @@ TB_V_FILES := $(wildcard ${VTB_DIR}/*.v)

# The following portion is depending on the EDA tools you are using, Please add them by yourself according to your EDA vendors

HAVE_VCS := $(shell type -p vcs 2> /dev/null)
HAVE_NCVERILOG := $(shell type -p ncverilog 2> /dev/null)
HAVE_IVERILOG := $(shell type -p iverilog 2> /dev/null)

SIM_TOOL := #To-ADD: to add the simulatoin tool
SIM_TOOL := iverilog # this is a free solution here to use iverilog to compile the code

SIM_OPTIONS := #To-ADD: to add the simulatoin tool options 
ifdef HAVE_IVERILOG
	SIM_TOOL := iverilog # this is a free solution here to use iverilog to compile the code
endif
ifdef HAVE_NCVERILOG
	SIM_TOOL := ncverilog
endif
ifdef HAVE_VCS
	SIM_TOOL := vcs
endif

SIM_OPTIONS := -o vvp.exec -I "${VSRC_DIR}/core/" -I "${VSRC_DIR}/perips/" -D DISABLE_SV_ASSERTION=1 -g2005 
 # This is a free solution here to use iverilog to compile the code. Please NOTE!!!! 
 # 
 # Note: 
 # Here we add a macro "DISABLE_SV_ASSERTION" to disable the system-verilog coded 
 # assertion in the RTL code because iverilog cannot support that syntax, if you
 # use other EDA tools which support the systemverilog, you should not add this macro "DISABLE_SV_ASSERTION".
 # 
 # Here we didnt add macro "ENABLE_TB_FORCE"
 # that macro was used to enable the random interrupt and bus-error insertion to make
 # more intensive test in e200_opensource/tb/tb_top.v.
 # Although the test become more intensive, the drawback is it makes the regression 
 # simulation running very slower, so by default now it is turned off.
 # If you want to turn on them without caring the the regression speed,
 # you can just add macro `ENABLE_TB_FORCE` here in command line.
SIM_OPTIONS := #To-ADD: to add the simulatoin tool options 
#SIM_OPTIONS := -o vvp.exec -I "${VSRC_DIR}/core/" -I "${VSRC_DIR}/perips/" -D DISABLE_SV_ASSERTION=1 -g2005 


ifdef HAVE_IVERILOG
	SIM_OPTIONS := -o vvp.exec -I "${VSRC_DIR}/core/" -I "${VSRC_DIR}/perips/" -D DISABLE_SV_ASSERTION=1 -g2005
	# This is a free solution here to use iverilog to compile the code. Please NOTE!!!! 
	# 
	# Note: 
	# Here we add a macro "DISABLE_SV_ASSERTION" to disable the system-verilog coded 
	# assertion in the RTL code because iverilog cannot support that syntax, if you
	# use other EDA tools which support the systemverilog, you should not add this macro "DISABLE_SV_ASSERTION".
	# 
	# Here we didnt add macro "ENABLE_TB_FORCE"
	# that macro was used to enable the random interrupt and bus-error insertion to make
	# more intensive test in e200_opensource/tb/tb_top.v.
	# Although the test become more intensive, the drawback is it makes the regression 
	# simulation running very slower, so by default now it is turned off.
	# If you want to turn on them without caring the the regression speed,
	# you can just add macro `ENABLE_TB_FORCE` here in command line.
endif
ifdef HAVE_NCVERILOG
	SIM_OPTIONS := -64bit +incdir+"${VSRC_DIR}/core/" +incdir+"${VSRC_DIR}/perips/" +sv +nctimescale+1ns/1ns +access+r +nclicq
endif
ifdef HAVE_VCS
	SIM_OPTIONS := -full64 +rad +v2k -sverilog +nospecify +notimingcheck -timescale=1ns/1ns -top tb_top +incdir+"${VSRC_DIR}/core/" +incdir+"${VSRC_DIR}/perips/"
endif


SIM_EXEC := #To-ADD: to add the simulatoin executable

ifdef HAVE_IVERILOG
#SIM_EXEC := vvp ${RUN_DIR}/vvp.exec -none # The free vvp is tooooo slow to run, so just comment it out, and replaced with the fake way below
SIM_EXEC := echo "Test Result Summary: PASS" # This is a fake run to just direct print PASS info to the log, the user need to actually replace it to the real EDA command
	SIM_EXEC := echo "Test Result Summary: PASS" # This is a fake run to just direct print PASS info to the log, the user need to actually replace it to the real EDA command
endif
ifdef HAVE_NCVERILOG
	SIM_EXEC := echo "Test Result Summary: PASS" # This is a fake run to just direct print PASS info to the log, the user need to actually replace it to the real EDA command
endif
ifdef HAVE_VCS
	SIM_EXEC := ${RUN_DIR}/simv # snps vcs simulation
endif

WAV_TOOL := #To-ADD: to add the waveform tool
WAV_OPTIONS := #To-ADD: to add the waveform tool options 
Expand All@@ -48,7 +80,7 @@ all: run

compile.flg: ${RTL_V_FILES} ${TB_V_FILES}
	@-rm -rf compile.flg
	${SIM_TOOL} ${SIM_OPTIONS} ${RTL_V_FILES} ${TB_V_FILES} ;
	${SIM_TOOL} ${SIM_OPTIONS} ${RTL_V_FILES} ${TB_V_FILES} ;
	touch compile.flg

compile: compile.flg 
Expand Down

, 'i');
if (__m === '*' || __re.test(location.href)) {
// Auto-enable theater mode on YouTube
(function() {
function tryTheater() {
var btn = document.querySelector('button[aria-label="Theater mode"], ytd-player #player button[title="Theater mode"]');
if (btn && !btn.classList.contains('activated')) {
btn.click();
}
}
// Try immediately
tryTheater();
// Try after navigation (SPA)
var lastUrl = location.href;
setInterval(function() {
if (location.href !== lastUrl) {
lastUrl = location.href;
setTimeout(tryTheater, 500);
}
}, 1000);
// Also try on player load
var observer = new MutationObserver(tryTheater);
observer.observe(document.body, { childList: true, subtree: true });
})();
}
} catch(__e) { console.warn('[Userscript:YouTube Theater Mode Default]', __e); }
})();
(function(){
try {
var __m = "*";
var __re = new RegExp('^' + ".*" + '
vsim/Makefile: fix build command in some case by vowstar · Pull Request #40 · SI-RISCV/e200_opensource · GitHub
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This repository was archived by the owner on Mar 24, 2021. It is now read-only.

vsim/Makefile: fix build command in some case#40
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#40
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1 change: 1 addition & 0 deletions
vsim/Makefile

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -27,6 +27,7 @@ install:
	cp ${SIM_DIR}/../rtl/${core_name} ${SIM_DIR}/install/rtl -rf

${RUN_DIR}:
	[[ -d install ]] || make install
	mkdir -p ${RUN_DIR}
	rm -f ${RUN_DIR}/Makefile
	ln -s ${SIM_DIR}/bin/run.makefile ${RUN_DIR}/Makefile
Expand Down

70 changes: 51 additions & 19 deletions
vsim/bin/run.makefile

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -14,31 +14,63 @@ TB_V_FILES := $(wildcard ${VTB_DIR}/*.v)

# The following portion is depending on the EDA tools you are using, Please add them by yourself according to your EDA vendors

HAVE_VCS := $(shell type -p vcs 2> /dev/null)
HAVE_NCVERILOG := $(shell type -p ncverilog 2> /dev/null)
HAVE_IVERILOG := $(shell type -p iverilog 2> /dev/null)

SIM_TOOL := #To-ADD: to add the simulatoin tool
SIM_TOOL := iverilog # this is a free solution here to use iverilog to compile the code

SIM_OPTIONS := #To-ADD: to add the simulatoin tool options 
ifdef HAVE_IVERILOG
	SIM_TOOL := iverilog # this is a free solution here to use iverilog to compile the code
endif
ifdef HAVE_NCVERILOG
	SIM_TOOL := ncverilog
endif
ifdef HAVE_VCS
	SIM_TOOL := vcs
endif

SIM_OPTIONS := -o vvp.exec -I "${VSRC_DIR}/core/" -I "${VSRC_DIR}/perips/" -D DISABLE_SV_ASSERTION=1 -g2005 
 # This is a free solution here to use iverilog to compile the code. Please NOTE!!!! 
 # 
 # Note: 
 # Here we add a macro "DISABLE_SV_ASSERTION" to disable the system-verilog coded 
 # assertion in the RTL code because iverilog cannot support that syntax, if you
 # use other EDA tools which support the systemverilog, you should not add this macro "DISABLE_SV_ASSERTION".
 # 
 # Here we didnt add macro "ENABLE_TB_FORCE"
 # that macro was used to enable the random interrupt and bus-error insertion to make
 # more intensive test in e200_opensource/tb/tb_top.v.
 # Although the test become more intensive, the drawback is it makes the regression 
 # simulation running very slower, so by default now it is turned off.
 # If you want to turn on them without caring the the regression speed,
 # you can just add macro `ENABLE_TB_FORCE` here in command line.
SIM_OPTIONS := #To-ADD: to add the simulatoin tool options 
#SIM_OPTIONS := -o vvp.exec -I "${VSRC_DIR}/core/" -I "${VSRC_DIR}/perips/" -D DISABLE_SV_ASSERTION=1 -g2005 


ifdef HAVE_IVERILOG
	SIM_OPTIONS := -o vvp.exec -I "${VSRC_DIR}/core/" -I "${VSRC_DIR}/perips/" -D DISABLE_SV_ASSERTION=1 -g2005
	# This is a free solution here to use iverilog to compile the code. Please NOTE!!!! 
	# 
	# Note: 
	# Here we add a macro "DISABLE_SV_ASSERTION" to disable the system-verilog coded 
	# assertion in the RTL code because iverilog cannot support that syntax, if you
	# use other EDA tools which support the systemverilog, you should not add this macro "DISABLE_SV_ASSERTION".
	# 
	# Here we didnt add macro "ENABLE_TB_FORCE"
	# that macro was used to enable the random interrupt and bus-error insertion to make
	# more intensive test in e200_opensource/tb/tb_top.v.
	# Although the test become more intensive, the drawback is it makes the regression 
	# simulation running very slower, so by default now it is turned off.
	# If you want to turn on them without caring the the regression speed,
	# you can just add macro `ENABLE_TB_FORCE` here in command line.
endif
ifdef HAVE_NCVERILOG
	SIM_OPTIONS := -64bit +incdir+"${VSRC_DIR}/core/" +incdir+"${VSRC_DIR}/perips/" +sv +nctimescale+1ns/1ns +access+r +nclicq
endif
ifdef HAVE_VCS
	SIM_OPTIONS := -full64 +rad +v2k -sverilog +nospecify +notimingcheck -timescale=1ns/1ns -top tb_top +incdir+"${VSRC_DIR}/core/" +incdir+"${VSRC_DIR}/perips/"
endif


SIM_EXEC := #To-ADD: to add the simulatoin executable

ifdef HAVE_IVERILOG
#SIM_EXEC := vvp ${RUN_DIR}/vvp.exec -none # The free vvp is tooooo slow to run, so just comment it out, and replaced with the fake way below
SIM_EXEC := echo "Test Result Summary: PASS" # This is a fake run to just direct print PASS info to the log, the user need to actually replace it to the real EDA command
	SIM_EXEC := echo "Test Result Summary: PASS" # This is a fake run to just direct print PASS info to the log, the user need to actually replace it to the real EDA command
endif
ifdef HAVE_NCVERILOG
	SIM_EXEC := echo "Test Result Summary: PASS" # This is a fake run to just direct print PASS info to the log, the user need to actually replace it to the real EDA command
endif
ifdef HAVE_VCS
	SIM_EXEC := ${RUN_DIR}/simv # snps vcs simulation
endif

WAV_TOOL := #To-ADD: to add the waveform tool
WAV_OPTIONS := #To-ADD: to add the waveform tool options 
Expand All@@ -48,7 +80,7 @@ all: run

compile.flg: ${RTL_V_FILES} ${TB_V_FILES}
	@-rm -rf compile.flg
	${SIM_TOOL} ${SIM_OPTIONS} ${RTL_V_FILES} ${TB_V_FILES} ;
	${SIM_TOOL} ${SIM_OPTIONS} ${RTL_V_FILES} ${TB_V_FILES} ;
	touch compile.flg

compile: compile.flg 
Expand Down

, 'i');
if (__m === '*' || __re.test(location.href)) {
// Remove or un-stick sticky/fixed headers that block content
(function() {
function unstick() {
document.querySelectorAll('header, nav, [role="banner"], .header, .navbar, .sticky, .fixed-top, [style*="position: fixed"], [style*="position:sticky"]').forEach(function(el) {
if (el.style.position === 'fixed' || el.style.position === 'sticky' || getComputedStyle(el).position === 'fixed' || getComputedStyle(el).position === 'sticky') {
el.style.position = 'static';
el.style.top = 'auto';
el.style.zIndex = 'auto';
}
});
}
unstick();
var observer = new MutationObserver(unstick);
observer.observe(document.body, { childList: true, subtree: true, attributes: true, attributeFilter: ['style', 'class'] });
})();
}
} catch(__e) { console.warn('[Userscript:Kill Sticky Headers]', __e); }
})();
(function(){
try {
var __m = "*";
var __re = new RegExp('^' + ".*" + '
vsim/Makefile: fix build command in some case by vowstar · Pull Request #40 · SI-RISCV/e200_opensource · GitHub
Skip to content

This repository was archived by the owner on Mar 24, 2021. It is now read-only.

vsim/Makefile: fix build command in some case#40
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commit into

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Choose a base branch

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#40
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1 change: 1 addition & 0 deletions
vsim/Makefile

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -27,6 +27,7 @@ install:
	cp ${SIM_DIR}/../rtl/${core_name} ${SIM_DIR}/install/rtl -rf

${RUN_DIR}:
	[[ -d install ]] || make install
	mkdir -p ${RUN_DIR}
	rm -f ${RUN_DIR}/Makefile
	ln -s ${SIM_DIR}/bin/run.makefile ${RUN_DIR}/Makefile
Expand Down

70 changes: 51 additions & 19 deletions
vsim/bin/run.makefile

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -14,31 +14,63 @@ TB_V_FILES := $(wildcard ${VTB_DIR}/*.v)

# The following portion is depending on the EDA tools you are using, Please add them by yourself according to your EDA vendors

HAVE_VCS := $(shell type -p vcs 2> /dev/null)
HAVE_NCVERILOG := $(shell type -p ncverilog 2> /dev/null)
HAVE_IVERILOG := $(shell type -p iverilog 2> /dev/null)

SIM_TOOL := #To-ADD: to add the simulatoin tool
SIM_TOOL := iverilog # this is a free solution here to use iverilog to compile the code

SIM_OPTIONS := #To-ADD: to add the simulatoin tool options 
ifdef HAVE_IVERILOG
	SIM_TOOL := iverilog # this is a free solution here to use iverilog to compile the code
endif
ifdef HAVE_NCVERILOG
	SIM_TOOL := ncverilog
endif
ifdef HAVE_VCS
	SIM_TOOL := vcs
endif

SIM_OPTIONS := -o vvp.exec -I "${VSRC_DIR}/core/" -I "${VSRC_DIR}/perips/" -D DISABLE_SV_ASSERTION=1 -g2005 
 # This is a free solution here to use iverilog to compile the code. Please NOTE!!!! 
 # 
 # Note: 
 # Here we add a macro "DISABLE_SV_ASSERTION" to disable the system-verilog coded 
 # assertion in the RTL code because iverilog cannot support that syntax, if you
 # use other EDA tools which support the systemverilog, you should not add this macro "DISABLE_SV_ASSERTION".
 # 
 # Here we didnt add macro "ENABLE_TB_FORCE"
 # that macro was used to enable the random interrupt and bus-error insertion to make
 # more intensive test in e200_opensource/tb/tb_top.v.
 # Although the test become more intensive, the drawback is it makes the regression 
 # simulation running very slower, so by default now it is turned off.
 # If you want to turn on them without caring the the regression speed,
 # you can just add macro `ENABLE_TB_FORCE` here in command line.
SIM_OPTIONS := #To-ADD: to add the simulatoin tool options 
#SIM_OPTIONS := -o vvp.exec -I "${VSRC_DIR}/core/" -I "${VSRC_DIR}/perips/" -D DISABLE_SV_ASSERTION=1 -g2005 


ifdef HAVE_IVERILOG
	SIM_OPTIONS := -o vvp.exec -I "${VSRC_DIR}/core/" -I "${VSRC_DIR}/perips/" -D DISABLE_SV_ASSERTION=1 -g2005
	# This is a free solution here to use iverilog to compile the code. Please NOTE!!!! 
	# 
	# Note: 
	# Here we add a macro "DISABLE_SV_ASSERTION" to disable the system-verilog coded 
	# assertion in the RTL code because iverilog cannot support that syntax, if you
	# use other EDA tools which support the systemverilog, you should not add this macro "DISABLE_SV_ASSERTION".
	# 
	# Here we didnt add macro "ENABLE_TB_FORCE"
	# that macro was used to enable the random interrupt and bus-error insertion to make
	# more intensive test in e200_opensource/tb/tb_top.v.
	# Although the test become more intensive, the drawback is it makes the regression 
	# simulation running very slower, so by default now it is turned off.
	# If you want to turn on them without caring the the regression speed,
	# you can just add macro `ENABLE_TB_FORCE` here in command line.
endif
ifdef HAVE_NCVERILOG
	SIM_OPTIONS := -64bit +incdir+"${VSRC_DIR}/core/" +incdir+"${VSRC_DIR}/perips/" +sv +nctimescale+1ns/1ns +access+r +nclicq
endif
ifdef HAVE_VCS
	SIM_OPTIONS := -full64 +rad +v2k -sverilog +nospecify +notimingcheck -timescale=1ns/1ns -top tb_top +incdir+"${VSRC_DIR}/core/" +incdir+"${VSRC_DIR}/perips/"
endif


SIM_EXEC := #To-ADD: to add the simulatoin executable

ifdef HAVE_IVERILOG
#SIM_EXEC := vvp ${RUN_DIR}/vvp.exec -none # The free vvp is tooooo slow to run, so just comment it out, and replaced with the fake way below
SIM_EXEC := echo "Test Result Summary: PASS" # This is a fake run to just direct print PASS info to the log, the user need to actually replace it to the real EDA command
	SIM_EXEC := echo "Test Result Summary: PASS" # This is a fake run to just direct print PASS info to the log, the user need to actually replace it to the real EDA command
endif
ifdef HAVE_NCVERILOG
	SIM_EXEC := echo "Test Result Summary: PASS" # This is a fake run to just direct print PASS info to the log, the user need to actually replace it to the real EDA command
endif
ifdef HAVE_VCS
	SIM_EXEC := ${RUN_DIR}/simv # snps vcs simulation
endif

WAV_TOOL := #To-ADD: to add the waveform tool
WAV_OPTIONS := #To-ADD: to add the waveform tool options 
Expand All@@ -48,7 +80,7 @@ all: run

compile.flg: ${RTL_V_FILES} ${TB_V_FILES}
	@-rm -rf compile.flg
	${SIM_TOOL} ${SIM_OPTIONS} ${RTL_V_FILES} ${TB_V_FILES} ;
	${SIM_TOOL} ${SIM_OPTIONS} ${RTL_V_FILES} ${TB_V_FILES} ;
	touch compile.flg

compile: compile.flg 
Expand Down

, 'i');
if (__m === '*' || __re.test(location.href)) {
// Universal Dark Mode - works on any site
(function() {
var enabled = true;
function applyDarkMode() {
if (!enabled) return;
// Create style element if it doesn't exist
var style = document.getElementById('universal-dark-mode-style');
if (!style) {
style = document.createElement('style');
style.id = 'universal-dark-mode-style';
document.head.appendChild(style);
}
// Dark mode CSS - inverts colors but preserves images/video
style.textContent = '
/* Invert everything except media */
html {
filter: invert(1) hue-rotate(180deg) !important;
background: #1a1a2e !important;
}
/* Restore images, videos, iframes, canvas */
img, video, iframe, canvas, svg, picture, [style*="background-image"] {
filter: invert(1) hue-rotate(180deg) !important;
}
/* Preserve specific elements that should not be inverted */
.no-dark-mode, .no-dark-mode *,
[data-theme="light"], [data-theme="light"],
.ace_editor, .ace_editor *,
.CodeMirror, .CodeMirror *,
.monaco-editor, .monaco-editor *,
.markdown-body pre, .markdown-body pre *,
.highlight, .highlight *,
pre code, pre code * {
filter: none !important;
}
/* Fix common UI elements */
.modal, .popup, .dropdown-menu, .tooltip, .popover {
filter: invert(1) hue-rotate(180deg) !important;
background: #2d2d44 !important;
border-color: #444 !important;
}
/* Scrollbars */
::-webkit-scrollbar { background: #1a1a2e !important; }
::-webkit-scrollbar-thumb { background: #444 !important; }
::-webkit-scrollbar-thumb:hover { background: #555 !important; }
/* Selection */
::selection { background: #4ecdc4 !important; color: #1a1a2e !important; }
::-moz-selection { background: #4ecdc4 !important; color: #1a1a2e !important; }
';
}
function removeDarkMode() {
var style = document.getElementById('universal-dark-mode-style');
if (style) style.remove();
}
// Toggle with Alt+Shift+D
document.addEventListener('keydown', function(e) {
if (e.altKey && e.shiftKey && e.key === 'D') {
e.preventDefault();
enabled = !enabled;
if (enabled) {
applyDarkMode();
console.log('[Universal Dark Mode] Enabled');
} else {
removeDarkMode();
console.log('[Universal Dark Mode] Disabled');
}
}
});
// Apply on load
applyDarkMode();
// Re-apply on dynamic content
var observer = new MutationObserver(function(mutations) {
if (enabled && !document.getElementById('universal-dark-mode-style')) {
applyDarkMode();
}
});
observer.observe(document.head, { childList: true });
console.log('[Universal Dark Mode] Loaded - Press Alt+Shift+D to toggle');
})();
}
} catch(__e) { console.warn('[Userscript:Universal Dark Mode]', __e); }
})();
})();
vsim/Makefile: fix build command in some case by vowstar · Pull Request #40 · SI-RISCV/e200_opensource · GitHub
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This repository was archived by the owner on Mar 24, 2021. It is now read-only.

vsim/Makefile: fix build command in some case#40
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1 change: 1 addition & 0 deletions
vsim/Makefile

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Original file line numberDiff line numberDiff line change
Expand Up@@ -27,6 +27,7 @@ install:
	cp ${SIM_DIR}/../rtl/${core_name} ${SIM_DIR}/install/rtl -rf

${RUN_DIR}:
	[[ -d install ]] || make install
	mkdir -p ${RUN_DIR}
	rm -f ${RUN_DIR}/Makefile
	ln -s ${SIM_DIR}/bin/run.makefile ${RUN_DIR}/Makefile
Expand Down

70 changes: 51 additions & 19 deletions
vsim/bin/run.makefile

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Original file line numberDiff line numberDiff line change
Expand Up@@ -14,31 +14,63 @@ TB_V_FILES := $(wildcard ${VTB_DIR}/*.v)

# The following portion is depending on the EDA tools you are using, Please add them by yourself according to your EDA vendors

HAVE_VCS := $(shell type -p vcs 2> /dev/null)
HAVE_NCVERILOG := $(shell type -p ncverilog 2> /dev/null)
HAVE_IVERILOG := $(shell type -p iverilog 2> /dev/null)

SIM_TOOL := #To-ADD: to add the simulatoin tool
SIM_TOOL := iverilog # this is a free solution here to use iverilog to compile the code

SIM_OPTIONS := #To-ADD: to add the simulatoin tool options 
ifdef HAVE_IVERILOG
	SIM_TOOL := iverilog # this is a free solution here to use iverilog to compile the code
endif
ifdef HAVE_NCVERILOG
	SIM_TOOL := ncverilog
endif
ifdef HAVE_VCS
	SIM_TOOL := vcs
endif

SIM_OPTIONS := -o vvp.exec -I "${VSRC_DIR}/core/" -I "${VSRC_DIR}/perips/" -D DISABLE_SV_ASSERTION=1 -g2005 
 # This is a free solution here to use iverilog to compile the code. Please NOTE!!!! 
 # 
 # Note: 
 # Here we add a macro "DISABLE_SV_ASSERTION" to disable the system-verilog coded 
 # assertion in the RTL code because iverilog cannot support that syntax, if you
 # use other EDA tools which support the systemverilog, you should not add this macro "DISABLE_SV_ASSERTION".
 # 
 # Here we didnt add macro "ENABLE_TB_FORCE"
 # that macro was used to enable the random interrupt and bus-error insertion to make
 # more intensive test in e200_opensource/tb/tb_top.v.
 # Although the test become more intensive, the drawback is it makes the regression 
 # simulation running very slower, so by default now it is turned off.
 # If you want to turn on them without caring the the regression speed,
 # you can just add macro `ENABLE_TB_FORCE` here in command line.
SIM_OPTIONS := #To-ADD: to add the simulatoin tool options 
#SIM_OPTIONS := -o vvp.exec -I "${VSRC_DIR}/core/" -I "${VSRC_DIR}/perips/" -D DISABLE_SV_ASSERTION=1 -g2005 


ifdef HAVE_IVERILOG
	SIM_OPTIONS := -o vvp.exec -I "${VSRC_DIR}/core/" -I "${VSRC_DIR}/perips/" -D DISABLE_SV_ASSERTION=1 -g2005
	# This is a free solution here to use iverilog to compile the code. Please NOTE!!!! 
	# 
	# Note: 
	# Here we add a macro "DISABLE_SV_ASSERTION" to disable the system-verilog coded 
	# assertion in the RTL code because iverilog cannot support that syntax, if you
	# use other EDA tools which support the systemverilog, you should not add this macro "DISABLE_SV_ASSERTION".
	# 
	# Here we didnt add macro "ENABLE_TB_FORCE"
	# that macro was used to enable the random interrupt and bus-error insertion to make
	# more intensive test in e200_opensource/tb/tb_top.v.
	# Although the test become more intensive, the drawback is it makes the regression 
	# simulation running very slower, so by default now it is turned off.
	# If you want to turn on them without caring the the regression speed,
	# you can just add macro `ENABLE_TB_FORCE` here in command line.
endif
ifdef HAVE_NCVERILOG
	SIM_OPTIONS := -64bit +incdir+"${VSRC_DIR}/core/" +incdir+"${VSRC_DIR}/perips/" +sv +nctimescale+1ns/1ns +access+r +nclicq
endif
ifdef HAVE_VCS
	SIM_OPTIONS := -full64 +rad +v2k -sverilog +nospecify +notimingcheck -timescale=1ns/1ns -top tb_top +incdir+"${VSRC_DIR}/core/" +incdir+"${VSRC_DIR}/perips/"
endif


SIM_EXEC := #To-ADD: to add the simulatoin executable

ifdef HAVE_IVERILOG
#SIM_EXEC := vvp ${RUN_DIR}/vvp.exec -none # The free vvp is tooooo slow to run, so just comment it out, and replaced with the fake way below
SIM_EXEC := echo "Test Result Summary: PASS" # This is a fake run to just direct print PASS info to the log, the user need to actually replace it to the real EDA command
	SIM_EXEC := echo "Test Result Summary: PASS" # This is a fake run to just direct print PASS info to the log, the user need to actually replace it to the real EDA command
endif
ifdef HAVE_NCVERILOG
	SIM_EXEC := echo "Test Result Summary: PASS" # This is a fake run to just direct print PASS info to the log, the user need to actually replace it to the real EDA command
endif
ifdef HAVE_VCS
	SIM_EXEC := ${RUN_DIR}/simv # snps vcs simulation
endif

WAV_TOOL := #To-ADD: to add the waveform tool
WAV_OPTIONS := #To-ADD: to add the waveform tool options 
Expand All@@ -48,7 +80,7 @@ all: run

compile.flg: ${RTL_V_FILES} ${TB_V_FILES}
	@-rm -rf compile.flg
	${SIM_TOOL} ${SIM_OPTIONS} ${RTL_V_FILES} ${TB_V_FILES} ;
	${SIM_TOOL} ${SIM_OPTIONS} ${RTL_V_FILES} ${TB_V_FILES} ;
	touch compile.flg

compile: compile.flg 
Expand Down