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1. Asynchronous_FIFOAsynchronous_FIFOPublic

   This project contains Design and UVM Verification of Asynchronous FIFO in System Verilog

   SystemVerilog 4 1

2. UARTUARTPublic

   Design and Verification of UART using class based verification and UVM

   SystemVerilog 2

3. Sidshx/LLC-cache-simulatorSidshx/LLC-cache-simulatorPublic

   A SystemVerilog-based simulation and design of a Last Level Cache (LLC) implementing the MESI protocol, featuring Pseudo-LRU replacement, multi-mode simulations, and comprehensive testing strategie…

   SystemVerilog 17 2

4. sk20052001/CA_RISCVsk20052001/CA_RISCVPublic

   Simulation of RISC-V architecture

   Assembly 1

5. HWforAI_MLHWforAI_MLPublic

   Verilog 1