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1. RISC-V_Core_4_StageRISC-V_Core_4_StagePublic

   RISCV MYTH 4 stage pipelined core designed using TL-Verilog and supports RV32I base integer instruction set

   16 7

2. OpenSource_Physical_DesignOpenSource_Physical_DesignPublic

   This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK

   53 15

3. LowPowerLowPowerPublic

   Various low power labs using sky130

   Verilog 13 4

4. vsdip/vsdsram_sky130vsdip/vsdsram_sky130Public

   SourcePawn 41 11

5. vsdsram_caravelvsdsram_caravelPublic

   Forked from efabless/caravel_user_project

   https://caravel-user-project.readthedocs.io

   Verilog 2

6. FPGA_Design_Fabric_ArchitectureFPGA_Design_Fabric_ArchitecturePublic

   This repository contains all the information studied and created during the FPGA - Fabric, Design and Architecture workshop. It is primarily focused on a complete FPGA flow using the maximum open-s…

   44 9