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    Sidshx/README.md

    Hi 👋! My name is Siddesh
    A Digital Design & Verification Enthusiast! 🤖

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    GitHub Activity Snake

    Hello World!! 👋 I'm Siddesh Passionate about **Computer Architecture, Memory Hierarchy, RTL Design, and Verification methodologies**, with extensive hands-on experience. 🔹 Experience 🚀 Design Verification (RV32IMFDAC and Vector on SHAKTI SoC) | Vyoma Systems, IIT Madras - Developed **design verification test plans**, generating **500+ assembly test cases** for RV32IMFDAC on SHAKTI SoC. - Explored RV-Vector extension, debugged, and documented **open-source test generators**, creating **reconfigurable assembly tests**.
⚡ Hardware Accelerator: ALRESCHA | CASL, UMD - Designed in **Verilog HDL**, optimized **sparse matrix computations**, achieving a **20% throughput improvement**. 🔍 And diving deeper... 🚀

    Pinned Loading

    1. sk20052001/CA_RISCVsk20052001/CA_RISCVPublic

      Simulation of RISC-V architecture

      Assembly 1

    2. LLC-cache-simulatorLLC-cache-simulatorPublic

      A SystemVerilog-based simulation and design of a Last Level Cache (LLC) implementing the MESI protocol, featuring Pseudo-LRU replacement, multi-mode simulations, and comprehensive testing strategie…

      SystemVerilog 17 2

    3. siddharth23-8/32-bit-RISC-V-Cpu-Coresiddharth23-8/32-bit-RISC-V-Cpu-CorePublic

      Python 35 4

    4. uvm_autotb_pyuvm_autotb_pyPublic

      UVM AutoTB Python Generator which automatically generates UVM testbench skeleton files using Python and a YAML configuration.

      SystemVerilog 1

    5. Satya7733/Asynchronous_FIFOSatya7733/Asynchronous_FIFOPublic

      This project contains Design and UVM Verification of Asynchronous FIFO in System Verilog

      SystemVerilog 4 1

    6. CMOS-NOR-Gate_IITH-HackathonCMOS-NOR-Gate_IITH-HackathonPublic

      CMOS Implemented NOR Gate is designed using Synopsys custom design tools.