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    Tharunreddym/README.md

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    About

    I am an ASIC Verification and Embedded Validation Engineer focused on UVM testbenches, protocol validation, firmware testing, and Python automation.

    I have hands on automotive embedded validation experience from Bosch India, where I worked on UART, SPI, I2C, and CAN validation, regression automation, protocol debugging, and hardware software integration.

    I build ASIC verification projects using SystemVerilog, UVM, SVA, constrained random stimulus, scoreboards, reference models, functional coverage, and regression debug workflows.

    I am pursuing my Masters in Computer Engineering at the University of Cincinnati and targeting roles in ASIC verification, design verification, embedded validation, firmware testing, and system level debug.


    Technical Skills

    ASIC Verification

    SystemVerilogUVMSVAConstrained RandomFunctional CoverageScoreboardsReference Models

    Digital Systems

    VerilogAXI4RISC VRV32ISRAMDPI C

    Embedded Validation

    Embedded CSTM32FreeRTOSUARTSPII2CCANUDS

    Automation And Tools

    Pythonpytestpyserialpython canQuestaSimVCSVerdiGitLinux


    Featured ASIC Verification Projects

    AXI4 Memory Controller Verification

    Built a UVM environment for AXI4 slave memory controller verification with agents, monitors, SVA checks, and scoreboard based validation across all 5 AXI4 channels.

    Key validation areas

    Write addressWrite dataWrite responseRead addressRead dataBurst trafficBackpressure


    ProtocolChannelsMethodology

    RISC V Pipeline Verification

    Developed a UVM testbench for a 5 stage RV32I pipeline with constrained random instruction generation, scoreboard checking, assertions, and a C++ reference model through DPI C.

    Key validation areas

    ForwardingHazardsBranchesPipeline stallsALU operationsRegister writeback


    PipelineISAReference Model

    SRAM Subsystem Verification

    Built a UVM based SRAM verification environment with constrained random stimulus, SVA checks, and a shadow memory scoreboard for read and write data validation.

    Regression evidence

    22 simulations20 random seeds30K plus transactionsZero scoreboard mismatches84.3 percent peak coverage


    RegressionSeedsTransactions


    Featured Embedded Validation Projects

    FreeRTOS Deadline Validation

    Validated real time task behavior on STM32 with FreeRTOS using producer, processor, and monitor tasks. Added overload injection and Python based HIL style automation.

    Key validation areas

    Task timingDeadline missesOverload behaviorUART logspytest automation


    TestsPlatformRTOS

    UDS Diagnostic Validation Suite

    Built a Python based UDS diagnostic validation suite using python can, ISO TP, udsoncan, virtual CAN, and pytest regression tests.

    Key validation areas

    Diagnostic requestsPositive responsesNegative responsesVirtual CANECU simulation


    TestsProtocolBus

    Sensor Based Embedded Validation System

    Validated STM32 and AHT30 sensor communication over I2C with UART logging, SDA and SCL fault injection, and recovery behavior checks.

    Key validation areas

    I2C readsSensor dataUART logsFault injectionRecovery testing


    TestsProtocolSensor

    STM32 HIL Style Validation Bench

    Created a Python automation bench for STM32 firmware validation with live UART capture, log parsing, guided fault injection, pytest regression, and HTML CSV JSON reports.

    Key validation areas

    UART captureLog parsingFault injectionRegression reportsFirmware validation


    TestsReportsAutomation


    What I Work On

    classVerificationAndValidationEngineer:
name="Tharun R. Mopuru"location="Cincinnati, Ohio"education="Masters in Computer Engineering, University of Cincinnati"asic_verification= [
"UVM testbench development",
"SystemVerilog assertions",
"Constrained random stimulus",
"Scoreboards and reference models",
"Functional coverage",
"Regression debug"
]
embedded_validation= [
"Firmware validation",
"Protocol debugging",
"STM32 and FreeRTOS testing",
"UART SPI I2C CAN validation",
"Python automation",
"HIL style test flows"
]
target_roles= [
"ASIC Verification Engineer",
"Design Verification Engineer",
"Embedded Validation Engineer",
"Firmware Test Engineer"
]

    Pinned Loading

    1. riscv-pipeline-verificationriscv-pipeline-verificationPublic

      UVM-based verification environment for a 5-stage RV32I RISC-V pipeline using constrained-random testing, DPI-C golden reference modeling, assertions, scoreboarding, functional coverage, and 20-seed…

      SystemVerilog 2

    2. axi4-verificationaxi4-verificationPublic

      AXI4 Memory Controller UVM Verification Environment with real Siemens Questa seed-1 simulation logs, scoreboard checks, functional coverage summaries, and documented burst-read debug fix.

      SystemVerilog

    3. sram-uvm-verificationsram-uvm-verificationPublic

      SRAM subsystem verification using SystemVerilog UVM, SVA assertions, scoreboard, functional coverage, and 20-seed QuestaSim regression evidence from EDA Playground.

      SystemVerilog

    4. UDS-Diagnostic-Validation-SuiteUDS-Diagnostic-Validation-SuitePublic

      UDS diagnostic validation suite using python-can, ISO-TP, and udsoncan with a threaded ECU simulator and pytest transport coverage.

      Python 1 3

    5. FreeRTOS-Deadline-ValidationFreeRTOS-Deadline-ValidationPublic

      C

    6. STM32-HIL-Style-Validation-BenchSTM32-HIL-Style-Validation-BenchPublic

      Python