-
Notifications
You must be signed in to change notification settings - Fork 95
Pull requests: UCSBarchlab/PyRTL
Author
Label
Projects
Milestones
Reviews
Assignee
Sort
Pull requests list
Add
src parameter to WireVector, Output, and Register
#512
opened Aug 12, 2026 by
timsherwood
Contributor
Loading…
2 tasks done
Implement a language agnostic hardware representation
#404
opened Sep 21, 2021 by
RhysGretsch81
Loading…
Ability to import specific module from Verilog/model from BLIF without making its io the block's IO
#398
opened Jul 9, 2021 by
mdko
Contributor
Loading…
ProTip!
What’s not been updated in a month: updated:<2026-08-19.