Popular repositories Loading

1. Tile_RTL_to_GDSII_28nm_Synopsys Tile_RTL_to_GDSII_28nm_SynopsysPublic

   End-to-end RTL to GDSII ASIC physical design implementation at 28nm using Synopsys DC and ICC2 with full timing closure and DRC clean signoff.

   1

2. reg2reg_synthesis reg2reg_synthesisPublic

   Synthesis of reg2reg single module with basic gates using Synopsys Design Compiler

3. tools-installation tools-installationPublic