Skip to content
View VSJ001's full-sized avatar

Block or report VSJ001

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don’t include any personal information such as legal names or email addresses. Markdown is supported. This note will only be visible to you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
VSJ001/README.md

Vaishnavi Srikanth Joshi

MS Electrical and Computer Engineering at Northeastern University, Boston (May 2027). Concentration in Computer Systems and Software.

I work at the boundary between hardware and software: pipeline microarchitecture, cache-aware kernel optimization, GPU acceleration, distributed systems concurrency and embedded firmware. Most of my projects either model real hardware to make it observable or push real hardware to its memory-bandwidth ceiling.

Currently seeking Fall 2026 co-op roles in embedded firmware, computer architecture or hardware performance engineering.

Featured projects

ProjectStackHeadline
Cache-Aware and GPU-Accelerated SpMVCUDA, C, AVX2Hand-written warp-per-row kernel reaches 98-110% of A100 HBM2 peak, beating cuSPARSE by 24-56% on SuiteSparse matrices
NFS-Like Distributed File ServerRust, UDP RPCLease-based write locking with FIFO/RR/MLFQ/CFS lock-queue policies, fairness-vs-latency analysis
5-Stage Pipeline Microarchitecture SimulatorCIF/ID/EX/MEM/WB simulator with load-use stall detection, EX/MEM and MEM/WB forwarding, branch flush, direct-mapped icache/dcache
FairShare-WiFiPython, SimPyContextual UCB schedulers (PlainUCB, LinUCB, DLinUCB, DKernelUCB) beat FIFO by 16.5% on Jain's Fairness Index
FPGA Middleware for Power System SimulationPython, Vitis HLS, VivadoSimulink-to-RTL pipeline on Zynq-7000 achieving 5.5-6x speedup over Simulink with 1e-11 to 1e-12 numerical error
Mandelbrot: Serial / OpenMP / Hybrid MPI+OpenMPC, OpenMP, MPI27-config benchmark sweep, hybrid 4-rank x 2-thread reaches ~4.8x speedup over serial
Photoplethysmography Heart Rate MonitorArduino, ATmega328P, MAX30105Live PPG waveform on ST7735 TFT via I2C/SPI with finger-presence buzzer alerts

Tech I work with

AreaTools
LanguagesC, C++, Rust, Python, MATLAB
GPU / HPCCUDA, cuSPARSE, OpenMP, MPI, AVX2, Linux perf, nsight-compute
Hardware / FPGAVitis HLS, Vivado, Verilog, ATmega328P, Zynq-7000
EmbeddedI2C, SPI, UART, ADC, Arduino, MAX30105, ST7735
SystemsLinux, SLURM, UDP, RPC, distributed locking, scheduling
Build / DevOpsMakefile, Cargo, Git, Docker, FastAPI, Redis

Background

WhereWhatWhen
Northeastern UniversityMS ECE (Computer Systems and Software), GPA 3.882025-2027
Foxconn Hon Hai Technology IndiaGraduate Trainee Engineer (iPhone manufacturing launch)Nov 2023 - Oct 2024
Visvesvaraya Technological UniversityBE Electronics and Communication Engineering, GPA 3.112019-2023

Connect

@VSJ001's activity is private