riscv: add Sscpuutil extension support for frequency invariance

arch/riscv/Kconfig

@@ -934,6 +934,16 @@ config PORTABLE
 	select MMU
 	select OF
 
+
+config RISCV_ISA_SSCPUUTIL
+	bool "Sscucnt extension support for CPU Utilization Counter"
+	depends on RISCV && GENERIC_ARCH_TOPOLOGY && SMP
+	default y
+	help
+	  Adds support for the Sscucnt (CPU Utilization Counter) extension
+	  which provides hardware counters for scheduler frequency invariance.
+	  If you do not know what to do here, say Y.
+
 menu "Power management options"
 
 source "kernel/power/Kconfig"

arch/riscv/include/asm/csr.h

@@ -259,6 +259,8 @@
 #define CSR_HPMCOUNTER29	0xc1d
 #define CSR_HPMCOUNTER30	0xc1e
 #define CSR_HPMCOUNTER31	0xc1f
+#define CSR_CORECYC		0xc30
+#define CSR_ACTTIME		0xc31
 #define CSR_CYCLEH		0xc80
 #define CSR_TIMEH		0xc81
 #define CSR_INSTRETH		0xc82
@@ -291,6 +293,8 @@
 #define CSR_HPMCOUNTER29H	0xc9d
 #define CSR_HPMCOUNTER30H	0xc9e
 #define CSR_HPMCOUNTER31H	0xc9f
+#define CSR_CORECYCH		0xcb0
+#define CSR_ACTTIMEH		0xcb1
 
 #define CSR_SSCOUNTOVF		0xda0
 

arch/riscv/include/asm/hwcap.h

@@ -59,6 +59,7 @@
 #define RISCV_ISA_EXT_ZIFENCEI		41
 #define RISCV_ISA_EXT_ZIHPM		42
 #define RISCV_ISA_EXT_XTHEADMATRIX	43
+#define RISCV_ISA_EXT_SSCPUUTIL		44
 
 #define RISCV_ISA_EXT_MAX		64
 

arch/riscv/include/asm/topology.h

@@ -4,6 +4,49 @@
 
 #include <linux/arch_topology.h>
 
+#ifdef CONFIG_RISCV_ISA_SSCPUUTIL
+
+#include <asm/csr.h>
+
+#ifdef CONFIG_64BIT
+static inline u64 get_corecyc(void)
+{
+	return csr_read(CSR_CORECYC);
+}
+
+static inline u64 get_acttime(void)
+{
+	return csr_read(CSR_ACTTIME);
+}
+#else
+static inline u64 get_corecyc(void)
+{
+	u32 hi, lo;
+
+	do {
+		hi = csr_read(CSR_CORECYCH);
+		lo = csr_read(CSR_CORECYC);
+	} while (hi != csr_read(CSR_CORECYCH));
+
+	return ((u64)hi << 32) | lo;
+}
+
+static inline u64 get_acttime(void)
+{
+	u32 hi, lo;
+
+	do {
+		hi = csr_read(CSR_ACTTIMEH);
+		lo = csr_read(CSR_ACTTIME);
+	} while (hi != csr_read(CSR_ACTTIMEH));
+
+	return ((u64)hi << 32) | lo;
+}
+#endif /* CONFIG_64BIT */
+
+void update_freq_counters_refs(void);
+#endif /* CONFIG_RISCV_ISA_SSCPUUTIL */
+
 /* Replace task scheduler's default frequency-invariant accounting */
 #define arch_scale_freq_tick		topology_scale_freq_tick
 #define arch_set_freq_scale		topology_set_freq_scale

arch/riscv/kernel/Makefile

@@ -104,3 +104,5 @@ obj-$(CONFIG_ARCH_RV64ILP32)	+= compat_signal.o
 
 obj-$(CONFIG_64BIT)		+= pi/
 obj-$(CONFIG_ACPI)		+= acpi.o
+
+obj-$(CONFIG_RISCV_ISA_SSCPUUTIL)	+= topology.o

arch/riscv/kernel/cpufeature.c

@@ -177,6 +177,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
 	__RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA),
 	__RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA),
 	__RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
+	__RISCV_ISA_EXT_DATA(sscpuutil, RISCV_ISA_EXT_SSCPUUTIL),
 	__RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC),
 	__RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL),
 	__RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT),

arch/riscv/kernel/smpboot.c

@@ -33,6 +33,7 @@
 #include <asm/tlbflush.h>
 #include <asm/sections.h>
 #include <asm/smp.h>
+#include <asm/topology.h>
 #include <uapi/asm/hwcap.h>
 #include <asm/vector.h>
 
@@ -61,6 +62,9 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
 	if (max_cpus == 0)
 		return;
 
+	if (IS_ENABLED(CONFIG_RISCV_ISA_SSCPUUTIL))
+		update_freq_counters_refs();
+
 	for_each_possible_cpu(cpuid) {
 		if (cpuid == curr_cpuid)
 			continue;
@@ -246,6 +250,9 @@ asmlinkage __visible void smp_callin(void)
 
 	numa_add_cpu(curr_cpuid);
 	set_cpu_online(curr_cpuid, 1);
+
+	if (IS_ENABLED(CONFIG_RISCV_ISA_SSCPUUTIL))
+		update_freq_counters_refs();
 	check_unaligned_access(curr_cpuid);
 
 	if (has_vector()) {