All issues

Search results

Bad Header in hello_pl.c

Status: Open.

#71In Xilinx/Embedded-Design-Tutorials;

· mike0698 opened on Feb 11, 2026

ref_files Example 5: testapp_r5.c contains old DEVICE_ID definitions instead of BASE_ADDR for XPAR_XUARTPS_

Status: Open.

#69In Xilinx/Embedded-Design-Tutorials;

· ComplaintsDepartment opened on Oct 27, 2025

Hello World UART output garbled on Alveo U25

Status: Open.

#67In Xilinx/Embedded-Design-Tutorials;

· WafaaFadlelmula opened on Aug 20, 2025

timer_psled_r5.c is broken

Status: Open.

#65In Xilinx/Embedded-Design-Tutorials;

· sei-jgwohlbier opened on May 1, 2025

cdma_app.c does not work correctly

bugSomething isn't workingSomething isn't working

Status: Open.

#52In Xilinx/Embedded-Design-Tutorials;

· profroyk opened on Aug 9, 2024

using petalinux 2021.2 vitis 2021.2 image from eMMC (sd0) image.ub read by u-boot takes a long time (~19sec): Trying to load boot images from mmc0 286172648 bytes read in 18889 ms (14.4 MiB/s) how can i significantly increase transfer rate?

Status: Open.

#47In Xilinx/Embedded-Design-Tutorials;

· hudini87 opened on Aug 30, 2023

Fix links

Status: Open.

#42In Xilinx/Embedded-Design-Tutorials;

· ryanvergel opened on Feb 9, 2023

Zynq7000-EDT tutorial ref file/example3 directory missing

Status: Open.

#35In Xilinx/Embedded-Design-Tutorials;

· byoman opened on Jan 11, 2023

Wrong link for SmartLynq+

Status: Open.

#27In Xilinx/Embedded-Design-Tutorials;

· cholmber opened on May 9, 2022

need to uncheck "Generate SD card image" in "debuggable fsbl"

Status: Open.

#26In Xilinx/Embedded-Design-Tutorials;

· aeewlwong opened on Mar 31, 2022