KAUST Accelerated Connected Computing Lab

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1. mx-systolic-fpga mx-systolic-fpgaPublic

   MX Systolic Arrays on FPGAs

   SystemVerilog 12 2

2. zypr zyprPublic

   Code and documentation for the ZyPR project enabling high level design of partially reconfigured systems on AMD/Xilinx Zynq UltraScale+ FPGA SoCs.

   C 6

3. interfacer interfacerPublic

   Python 2

4. fp-versal-bench fp-versal-benchPublic

   FP performance on pipelined AI Engine vs DSP58

   C++

5. PRNGine PRNGinePublic

   Porting PRNGs to AMD Versal AIEs

   C++

6. mc-option-pricing-aie mc-option-pricing-aiePublic

   Monte Carlo based financial option pricer on AMD Versal AI Engines

   C++