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Name		Name	Last commit message	Last commit date
doc		doc
lib		lib
rtl/verilog		rtl/verilog
sim		sim
sw		sw
README.md		README.md

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Multi-threaded 32-bit Microprocessor Core

REVISION HISTORY

*R12.02 - Last development update for AEMB2. All development will shift to the next-gen core.

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Multi-threaded 32-bit embedded core family.

www.aeste.my/aemb

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