Please read this to understand the design.
To build the design and run sims with Verilator:
make allTo open waves with gtkwave:
make waveTo build for Xilinx FPGA Kintex 7:
make fpga| Name | Name | Last commit date | ||
|---|---|---|---|---|
Please read this to understand the design.
To build the design and run sims with Verilator:
make allTo open waves with gtkwave:
make waveTo build for Xilinx FPGA Kintex 7:
make fpga