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1. aneels3.github.ioaneels3.github.ioPublic

   CSS

2. AES-128AES-128Public

   Single pipeline AES 128 bit encryption using S-box as Look up table.

   Verilog 4 3

3. chipsalliance/riscv-dvchipsalliance/riscv-dvPublic

   Random instruction generator for RISC-V processor verification

   Python 1.3k 391

4. veribleveriblePublic

   Forked from chipsalliance/verible

   Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, and formatter.

   C++

5. pyvscpyvscPublic

   Forked from fvutils/pyvsc

   Python packages providing a library for Verification Stimulus and Coverage

   Python