Skip to content
View anlit75's full-sized avatar
14 followers · 0 following

Achievements

Achievement: Pull Sharkx3Achievement: QuickdrawAchievement: Pair ExtraordinaireAchievement: YOLOAchievement: Starstruck

Achievements

Achievement: Pull Sharkx3Achievement: QuickdrawAchievement: Pair ExtraordinaireAchievement: YOLOAchievement: Starstruck

Block or report anlit75

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don’t include any personal information such as legal names or email addresses. Markdown is supported. This note will only be visible to you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
anlit75/README.md

Ting-An Cheng (Anson)

Digital IC Design Verification Engineer (DV) & Open Source Enthusiast specializing in RTL design, verification, and automation.

Tech Stack

🚀 IC Design & Verification

UVMSystemVerilogVerilog

🛠️ Others

PythonC++DockerMakefileLaTeXGitSVNGitHub Actions

Featured Work

ProjectWhat it solvesTech StackLink
CCU-Thesis-LaTeX-TemplateStreamlines thesis and dissertation formatting for National Chung Cheng University students with a compliant LaTeX template.LaTeXDockerView Code
ChipForAllA Zero-Config Starter Kit for Open Source Silicon Design.VerilogMakefileDockerView Code
ADPLLImplements an All-Digital Phase-Locked Loop for precise clock synchronization in digital systems.VerilogView Code
RepoGalleryAutomates the creation of a personal portfolio website by aggregating GitHub repository data.PythonGitHub ActionsView Code

Connect

LinkedInEmailWebsite

Pinned Loading

  1. CCU-Thesis-LaTeX-TemplateCCU-Thesis-LaTeX-TemplatePublic template

    國立中正大學碩博士論文 LaTeX 模板 (Unofficial CCU Thesis LaTeX Template)。整合 Docker 與 GitHub Codespaces 提供開箱即用的零配置寫作環境。

    TeX 47 13

  2. ChipForAllChipForAllPublic template

    A Zero-Config Starter Kit for Open Source Silicon Design.

    Makefile

  3. ADPLLADPLLPublic

    All Digital Phase-Locked Loop (ADPLL)

    Verilog 39 8

  4. RepoGalleryRepoGalleryPublic

    Just fork & good to go! A beautiful showcase for all your GitHub repos.

    Python 5 6

  5. SV-TBLabSV-TBLabPublic

    SystemVerilog Testbench Workshop Lab

    SystemVerilog 3 2

  6. dv-agentic-systemdv-agentic-systemPublic

    A multi-agent framework designed specifically for Digital IC Design Verification.

    Python 2 2