SystemVerilog Verification Labs

🎓 Comprehensive SystemVerilog learning repository with practical examples, detailed documentation, and hands-on exercises.

📚 Overview

This repository contains a complete set of SystemVerilog verification labs covering fundamental to advanced topics. Each lab includes:

✅ Complete, runnable code examples
✅ Detailed README documentation
✅ Practical, real-world scenarios
✅ Icarus Verilog compatibility notes
✅ Best practices and common pitfalls

🗂️ Lab Structure

Lab 1A: Signed-Unsigned & Overflow

File:lab1_signed_unsigned.sv (6.2K)
Topics: bit vs logic, signed vs unsigned, X/Z states, overflow detection
Documentation:LAB1A_SIGNED_UNSIGNED_README.md

iverilog -g2012 -o lab1_signed_unsigned lab1_signed_unsigned.sv && vvp lab1_signed_unsigned

Lab 1B: Packed Arrays

File:lab1b_packed_array.sv (8.7K)
Topics: Multi-dimensional packed arrays, part-select, bitwise operations
Documentation:LAB1B_PACKED_ARRAY_README.md

iverilog -g2012 -o lab1b_packed_array lab1b_packed_array.sv && vvp lab1b_packed_array

Lab 1C: Unpacked Arrays

File:lab1c_unpacked_array.sv (12K)
Topics: 2D matrices, image processing simulation, row/column operations
Documentation:LAB1C_UNPACKED_ARRAY_README.md

iverilog -g2012 -o lab1c_unpacked_array lab1c_unpacked_array.sv && vvp lab1c_unpacked_array

Lab 1D: Associative Arrays

File:lab1d_unpacked_array.sv (19K)
Topics: Key-value storage, MAC address tables, sparse memory
Documentation:LAB1D_ASSOCIATIVE_ARRAY_README.md
⚠️Note: Icarus Verilog doesn't support associative arrays. Use Questa/VCS/Xcelium.

iverilog -g2012 -o lab1d_unpacked_array lab1d_unpacked_array.sv && vvp lab1d_unpacked_array

Lab 1E: Queue

File:lab1e_queue.sv (21K)
Topics: FIFO/LIFO buffers, push/pop operations, circular buffers, packet processing
Documentation:LAB1E_QUEUE_README.md

iverilog -g2012 -o lab1e_queue lab1e_queue.sv && vvp lab1e_queue

Lab 1F: Tasks and Functions

File:lab1f_tasks_functions.sv (16K)
Topics:
- ADC conversion function (real → 8-bit)
- Pulse generation task (clock-synchronized)
- Command execution task (ALU with queue)
- Enum, packed struct, automatic keyword
Documentation:LAB1F_TASKS_FUNCTIONS_README.md

iverilog -g2012 -o lab1f_tasks_functions lab1f_tasks_functions.sv && vvp lab1f_tasks_functions

🚀 Quick Start

Prerequisites

# Install Icarus Verilog (Ubuntu/Debian)
sudo apt-get install iverilog
# Install Icarus Verilog (Fedora)
sudo dnf install iverilog
# Verify installation
iverilog -v

Clone and Run

# Clone the repository
git clone https://github.com/anoshyn/verification.git
cd verification
# Run all labs
./run_all_labs.sh
# Or run individually
iverilog -g2012 -o lab1a_signed_unsigned lab1a_signed_unsigned.sv && vvp lab1a_signed_unsigned
iverilog -g2012 -o lab1c_unpacked_array lab1c_unpacked_array.sv && vvp lab1c_unpacked_array
iverilog -g2012 -o lab1e_queue lab1e_queue.sv && vvp lab1e_queue
iverilog -g2012 -o lab1f_tasks_functions lab1f_tasks_functions.sv && vvp lab1f_tasks_functions

Clean up

rm -f lab1a_signed_unsigned lab1b_packed_array lab1c_unpacked_array lab1d_unpacked_array lab1e_queue lab1f_tasks_functions

📖 Documentation

Summary Document

LAB1_SUMMARY.md - Complete overview of all labs with quick reference

Individual Lab READMEs

Each lab has detailed documentation covering:

Syntax and semantics
Practical examples
Best practices
Common pitfalls
Simulator compatibility notes

🎯 Learning Path

graph TD
A[Lab 1A: Data Types] --> B[Lab 1A Extra: Packed Arrays]
A --> C[Lab 1B: Unpacked Arrays]
C --> D[Lab 1C: Associative Arrays]
C --> E[Lab 1D: Queue]
E --> F[Lab 1F: Tasks & Functions]
F --> G[Future: Classes & OOP]
G --> H[Future: UVM Framework]

Recommended Order:

Lab 1A - Foundation: Data types, signed/unsigned
Lab 1B - Packed arrays for synthesis
Lab 1C - Unpacked arrays for testbenches
Lab 1D - Dynamic queues for verification
Lab 1E - Associative arrays (commercial simulators)
Lab 1F - Functions and tasks for modularity

🔑 Key Concepts Covered

Data Types

✅ bit, logic, logic signed, int
✅ 2-state vs 4-state (X/Z handling)
✅ Sign extension vs Zero extension
✅ Overflow detection and prevention

Array Types

Type	Size	Operations	Synthesis	Use Case
Packed	Fixed	Bitwise	✅ Yes	RTL design, ports
Unpacked	Fixed	Index	❌ No	Testbenches, memory
Associative	Dynamic	Key-value	❌ No	Lookup tables, sparse
Queue	Dynamic	Push/pop	❌ No	Buffers, FIFO/LIFO

Functions vs Tasks

Feature	Function	Task
Return value	✅ `return`	❌ Use `output`
Timing	❌ No `#delay`	✅ Can use timing
Zero time	✅ Always	❌ Can consume time
Use for	Calculations	Sequences

🛠️ Practical Examples

What You'll Build

Network Packet Buffer (Queue) - FIFO with priority insertion
Image Processing (Unpacked Array) - 2D pixel matrix manipulation
MAC Address Table (Associative) - Network switch simulation
ADC Converter (Function) - Real to digital conversion
Pulse Generator (Task) - Clock-synchronized signal generation
ALU with Command Queue (Task + Queue) - Command processor

💡 Best Practices

DO ✅

// Use appropriate typeslogicsigned [7:0] temperature; // For signed valuesbit [7:0] counter; // For unsigned, 2-state// Prevent overflowlogic [8:0] sum = a + b; // Extra bit for carry// Use automatic for reentrant codefunction automatic intcalc(inputint x);
// Local variables are automaticendfunction

DON'T ❌

// Mixing signed/unsigned without carelogic [7:0] a =-1; // Interpreted as 255!// Insufficient bits for resultlogic [7:0] sum =8'd200+8'd100; // Overflow!// Non-automatic for recursive functionsfunction intfactorial(inputint n); // Missing automatic!

🔧 Icarus Verilog Limitations

While Icarus Verilog is excellent for learning, some SystemVerilog features aren't supported:

❌ Not Supported:

Associative arrays
%p format specifier for queues
Queue of structs (workaround: separate queues)
Aggregate initialization '{1, 2, 3}
Queue comparison operators

✅ Workarounds Provided:

Manual iteration for queue display
Individual push_back() for initialization
Separate queues for struct fields

For full SystemVerilog support, use:

Synopsys VCS
Mentor Questa
Cadence Xcelium

📊 Statistics

Total Labs: 6 (+ extras)
Total Code: ~83K lines
Total Documentation: ~73K documentation
Code Examples: 100+
Practical Scenarios: 15+

🎓 Learning Outcomes

After completing these labs, you will be able to:

✅ Choose appropriate data types for signed/unsigned values
✅ Prevent and detect overflow conditions
✅ Use packed arrays for synthesizable RTL design
✅ Use unpacked arrays for testbench data structures
✅ Implement dynamic queues for FIFO/LIFO buffers
✅ Write functions for combinational logic
✅ Write tasks for sequential operations with timing
✅ Use enums and structs for clean code organization
✅ Build realistic verification testbenches

🚧 Future Labs (Coming Soon)

Lab 3: Classes and Object-Oriented Programming
Lab 4: Interfaces and Modports
Lab 5: Randomization and Constraints
Lab 6: Functional Coverage
Lab 7: Basic UVM Components
Lab 8: UVM Testbench Architecture

📚 Additional Resources

Official Documentation

Recommended Books

"SystemVerilog for Verification" by Chris Spear & Greg Tumbush
"SystemVerilog for Design" by Stuart Sutherland
"Writing Testbenches using SystemVerilog" by Janick Bergeron

Online Resources

🤝 Contributing

Contributions are welcome! Please feel free to:

Report issues
Suggest improvements
Add new examples
Fix documentation typos
Share your learning experience

📧 Contact

Author: Andrii
Repository:github.com/anoshyn/verification

📄 License

This project is for educational purposes. Feel free to use, modify, and share for learning SystemVerilog verification.

⭐ Show Your Support

If you find these labs helpful, please ⭐ star this repository!

Last Updated: 20 жовтня 2025 р.
SystemVerilog Standard: IEEE 1800-2012
Simulator: Icarus Verilog 12.0

Happy Learning! 🚀

Name		Name	Last commit message	Last commit date
LAB1A_SIGNED_UNSIGNED_README.md		LAB1A_SIGNED_UNSIGNED_README.md
LAB1B_PACKED_ARRAY_README.md		LAB1B_PACKED_ARRAY_README.md
LAB1C_UNPACKED_ARRAY_README.md		LAB1C_UNPACKED_ARRAY_README.md
LAB1D_ASSOCIATIVE_ARRAY_README.md		LAB1D_ASSOCIATIVE_ARRAY_README.md
LAB1E_QUEUE_README.md		LAB1E_QUEUE_README.md
LAB1F_TASKS_FUNCTIONS_README.md		LAB1F_TASKS_FUNCTIONS_README.md
LAB1_SUMMARY.md		LAB1_SUMMARY.md
README.md		README.md
lab1a_signed_unsigned.sv		lab1a_signed_unsigned.sv
lab1b_packed_array.sv		lab1b_packed_array.sv
lab1c_unpacked_array.sv		lab1c_unpacked_array.sv
lab1d_associative_array.sv		lab1d_associative_array.sv
lab1e_queue.sv		lab1e_queue.sv
lab1f_tasks_functions.sv		lab1f_tasks_functions.sv
run_all_labs.sh		run_all_labs.sh

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