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GH-49921: [C++] Bump xsimd to 14.2.0 - #49922
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pitrou
commented
May 6, 2026
@AntoinePrv Can you take a look at the CI failures? They seem related. |
AntoinePrv
commented
May 6, 2026
Yes, I am still waiting for the Msys2 build of xsimd to happen... |
pitrou
commented
May 6, 2026
There are failures on non-MSys2 builds, though: |
Perhaps it's this check that does not work on MSVC? Either we could add |
I think we should both 1) fix xsimd upstream anyway and 2) pass It seems xsimd should do something like this: #ifdef _MSVC_LANG
#defineXSIMD_CPP_LEVEL _MSVC_LANG
#else
#defineXSIMD_CPP_LEVEL __cplusplus
#endifand then use the (but xsimd could also use find-grained feature testing). |
Already sending a patch, but not sure I want to go through another round of xsimd releases |
pitrou
commented
May 6, 2026
Agreed, hence "pass /Zc:__cplusplus when building Arrow C++" as well 😉 |
pitrou
commented
May 6, 2026
Bloody protobuf fails building with |
pitrou
commented
May 6, 2026
Tiny syntax error that needs fixing: |
AntoinePrv
commented
May 6, 2026
@pitrou I'm not very proactively working on this until the msys2 xsimd build is live |
pitrou
commented
May 6, 2026
pitrou
commented
May 6, 2026
@github-actions crossbow submit -g cpp |
Revision: 89a1f7e Submitted crossbow builds: ursacomputing/crossbow @ actions-9c434593fe |
raulcd
commented
May 6, 2026
It's just a matter of waiting for their queue to update it: Based on experience when uploading Arrow it takes between 6 and 12 hours. Their CI seems to run several times a day and xsimd is already listed on the queue so it should be available "soon". |
raulcd
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Sorry, just thought about this, I am happy to merge as is.
Are we planning to bump this requirement later on when we improve the cpu detection feature?
arrow/cpp/cmake_modules/ThirdpartyToolchain.cmake
Lines 2855 to 2861 in 3d4ab3f
raulcd
commented
Jun 2, 2026
@github-actions crossbow submit wheelcp314 |
Revision: 8278222 Submitted crossbow builds: ursacomputing/crossbow @ actions-0d5b743af7 |
raulcd
commented
Jun 2, 2026
The Line 60 in 3d4ab3f and here: Line 10 in 3d4ab3f We should update to the same one we have on |
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raulcd
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ok, the latest fixed the CI failure. Current CI failures are unrelated, there's still some CI jobs finishing but if no surprises, I'll merge once they finish
AntoinePrv
commented
Jun 3, 2026
Thanks @raulcd ! Looks like this is ready now |
raulcd
commented
Jun 3, 2026
Merged! Thanks @AntoinePrv for following it up! |
After merging your PR, Conbench analyzed the 4 benchmarking runs that have been run so far on merge-commit a10f254. There were no benchmark performance regressions. 🎉 The full Conbench report has more details. It also includes information about 107 possible false positives for unstable benchmarks that are known to sometimes produce them. |
### Rationale for this change Use xsimd cpu feature instead of maitaining them here. Stacked on GH-49922. Should also handle issue from GH-30368. ### What changes are included in this PR? - Use xsimd for CPu feature detection, cache sizes are still using the same implementation - We are loosing CPU model name (which was unused) - Simplify CpuInfo (remove Pimpl pattern) ### Are these changes tested? in CI ### Are there any user-facing changes? No * GitHub Issue: #45331 Authored-by: AntoinePrv <AntoinePrv@users.noreply.github.com> Signed-off-by: Antoine Pitrou <antoine@python.org>
Rationale for this change
Fix SVE dynamic dispatch ODR violation xtensor-stack/xsimd#1311
What changes are included in this PR?
Bump version and cleanup backports.
Are these changes tested?
Yes, in CI.
Are there any user-facing changes?
No