[SVE] Implement scalable vectors in TVM by ekalda · Pull Request #16347 · apache/tvm

ekalda · 2024-01-04T10:02:00Z

This prototype is to accompany the open SVE RFC. It implements the design outlined in the RFC.

The main changes to the stack include:

tir.split can accept an expression with vscale as a factor
LoopVectorizer can create Ramp and Broadcast nodes with scalable lanes
BufferLoad and BufferStore nodes can accept an optional predicate which is created in LoopVectorizer
LLVM codegen can lower the scalable predicated vectors into llvm.masked.* intrinsics

The prototype is currently missing tir.tile~~and TVMScript parser support for predicates~~.

cbalint13

One minor nit to the code part.

cbalint13 · 2024-01-04T13:42:02Z

tir.split can accept an expression with vscale as a factor
LoopVectorizer can create Ramp and Broadcast nodes with scalable lanes
BufferLoad and BufferStore nodes can accept an optional predicate which is created in LoopVectorizer
LLVM codegen can lower the scalable predicated vectors into llvm.masked.* intrinsics
The prototype is currently missing tir.tile and TVMScript parser support for predicates.

Hi @ekalda ,

Very nice work !

I can't comment much, I think this implementation is a careful step toward SVE.
Will test this on some RVV CPU implementation to see a walk through the LLVM masked.* things.

ekalda · 2024-01-10T10:30:45Z

@tvm-bot rerun

This prototype is to accompany the open SVE RFC. It implements the design outlined in the RFC. The main changes to the stack include: 1. tir.split can accept an expression with vscale as a factor 2. LoopVectorizer can create Ramp and Broadcast nodes with scalable lanes 3. BufferLoad and BufferStore nodes can accept an optional predicate which is created in LoopVectorizer 4. LLVM codegen can lower the scalable predicated vectors into llvm.masked.* intrinsics The prototype is currently missing tir.tile and TVMScript parser support for predicates. Co-authored-by: Luke Hutton <luke.hutton@arm.com> Co-authored-by: Neil Hickey <neil.hickey@arm.com>

Change-Id: I7d90c8b8396ba7a2b609a91bea2fe5f599d5cb96

Change-Id: I2e994ffdacaf1dacdc875c2cfd62be433e6952c6

This commit adds support for expressing and printing buffer loads/stores in TVMScript. The buffer API has been extended with load and store methods which support passing a predicate parameter to BufferLoad/Store. When the printer encounters a predicated BufferLoad/Store, it will print with the .load/.store syntax as opposed to the shorthand [...] syntax as it is easier to represent predicates. Extending the functionality of vload and vstore was considered but they do not currently support expressing loading/storing of non-consecutive values and such a change will result in many changes across the codebase. An example of a predicated load and store in TVMScript: ``` A.load( [T.Ramp(i_0 * 4, 1, 4)], predicate=T.get_active_lane_mask("int1x4", i_0 * 4, 14), ) B.store( T.Broadcast(T.float32(1), 4), [T.Ramp(i_0 * 4, 1, 4)], predicate=T.get_active_lane_mask("int1x4", i_0 * 4, 14), ) ``` Change-Id: I1305c1b5d052ad109232604c6660e40d4a566dd6

Change-Id: I8a893377d7361bed8840a645fbaff81ab401ccb8

Plumb this argument through the te.split implementation to achieve feature parity with tir.split. Change-Id: I92707bc08e857b9fd5678153d998aeecebcce228

ekalda · 2024-01-04T10:02:00Z

This prototype is to accompany the open SVE RFC. It implements the design outlined in the RFC.

The main changes to the stack include:

tir.split can accept an expression with vscale as a factor
LoopVectorizer can create Ramp and Broadcast nodes with scalable lanes
BufferLoad and BufferStore nodes can accept an optional predicate which is created in LoopVectorizer
LLVM codegen can lower the scalable predicated vectors into llvm.masked.* intrinsics

The prototype is currently missing tir.tile~~and TVMScript parser support for predicates~~.

cbalint13

One minor nit to the code part.

cbalint13 · 2024-01-04T13:42:02Z

tir.split can accept an expression with vscale as a factor
LoopVectorizer can create Ramp and Broadcast nodes with scalable lanes
BufferLoad and BufferStore nodes can accept an optional predicate which is created in LoopVectorizer
LLVM codegen can lower the scalable predicated vectors into llvm.masked.* intrinsics
The prototype is currently missing tir.tile and TVMScript parser support for predicates.

Hi @ekalda ,

Very nice work !

I can't comment much, I think this implementation is a careful step toward SVE.
Will test this on some RVV CPU implementation to see a walk through the LLVM masked.* things.

ekalda · 2024-01-10T10:30:45Z

@tvm-bot rerun

This prototype is to accompany the open SVE RFC. It implements the design outlined in the RFC. The main changes to the stack include: 1. tir.split can accept an expression with vscale as a factor 2. LoopVectorizer can create Ramp and Broadcast nodes with scalable lanes 3. BufferLoad and BufferStore nodes can accept an optional predicate which is created in LoopVectorizer 4. LLVM codegen can lower the scalable predicated vectors into llvm.masked.* intrinsics The prototype is currently missing tir.tile and TVMScript parser support for predicates. Co-authored-by: Luke Hutton <luke.hutton@arm.com> Co-authored-by: Neil Hickey <neil.hickey@arm.com>

Change-Id: I7d90c8b8396ba7a2b609a91bea2fe5f599d5cb96

Change-Id: I2e994ffdacaf1dacdc875c2cfd62be433e6952c6

This commit adds support for expressing and printing buffer loads/stores in TVMScript. The buffer API has been extended with load and store methods which support passing a predicate parameter to BufferLoad/Store. When the printer encounters a predicated BufferLoad/Store, it will print with the .load/.store syntax as opposed to the shorthand [...] syntax as it is easier to represent predicates. Extending the functionality of vload and vstore was considered but they do not currently support expressing loading/storing of non-consecutive values and such a change will result in many changes across the codebase. An example of a predicated load and store in TVMScript: ``` A.load( [T.Ramp(i_0 * 4, 1, 4)], predicate=T.get_active_lane_mask("int1x4", i_0 * 4, 14), ) B.store( T.Broadcast(T.float32(1), 4), [T.Ramp(i_0 * 4, 1, 4)], predicate=T.get_active_lane_mask("int1x4", i_0 * 4, 14), ) ``` Change-Id: I1305c1b5d052ad109232604c6660e40d4a566dd6

Change-Id: I8a893377d7361bed8840a645fbaff81ab401ccb8

Plumb this argument through the te.split implementation to achieve feature parity with tir.split. Change-Id: I92707bc08e857b9fd5678153d998aeecebcce228

ekalda · 2024-01-04T10:02:00Z

This prototype is to accompany the open SVE RFC. It implements the design outlined in the RFC.

The main changes to the stack include:

tir.split can accept an expression with vscale as a factor
LoopVectorizer can create Ramp and Broadcast nodes with scalable lanes
BufferLoad and BufferStore nodes can accept an optional predicate which is created in LoopVectorizer
LLVM codegen can lower the scalable predicated vectors into llvm.masked.* intrinsics

The prototype is currently missing tir.tile~~and TVMScript parser support for predicates~~.

cbalint13

One minor nit to the code part.

cbalint13 · 2024-01-04T13:42:02Z

tir.split can accept an expression with vscale as a factor
LoopVectorizer can create Ramp and Broadcast nodes with scalable lanes
BufferLoad and BufferStore nodes can accept an optional predicate which is created in LoopVectorizer
LLVM codegen can lower the scalable predicated vectors into llvm.masked.* intrinsics
The prototype is currently missing tir.tile and TVMScript parser support for predicates.

Hi @ekalda ,

Very nice work !

I can't comment much, I think this implementation is a careful step toward SVE.
Will test this on some RVV CPU implementation to see a walk through the LLVM masked.* things.

ekalda · 2024-01-10T10:30:45Z

@tvm-bot rerun

This prototype is to accompany the open SVE RFC. It implements the design outlined in the RFC. The main changes to the stack include: 1. tir.split can accept an expression with vscale as a factor 2. LoopVectorizer can create Ramp and Broadcast nodes with scalable lanes 3. BufferLoad and BufferStore nodes can accept an optional predicate which is created in LoopVectorizer 4. LLVM codegen can lower the scalable predicated vectors into llvm.masked.* intrinsics The prototype is currently missing tir.tile and TVMScript parser support for predicates. Co-authored-by: Luke Hutton <luke.hutton@arm.com> Co-authored-by: Neil Hickey <neil.hickey@arm.com>

Change-Id: I7d90c8b8396ba7a2b609a91bea2fe5f599d5cb96

Change-Id: I2e994ffdacaf1dacdc875c2cfd62be433e6952c6

This commit adds support for expressing and printing buffer loads/stores in TVMScript. The buffer API has been extended with load and store methods which support passing a predicate parameter to BufferLoad/Store. When the printer encounters a predicated BufferLoad/Store, it will print with the .load/.store syntax as opposed to the shorthand [...] syntax as it is easier to represent predicates. Extending the functionality of vload and vstore was considered but they do not currently support expressing loading/storing of non-consecutive values and such a change will result in many changes across the codebase. An example of a predicated load and store in TVMScript: ``` A.load( [T.Ramp(i_0 * 4, 1, 4)], predicate=T.get_active_lane_mask("int1x4", i_0 * 4, 14), ) B.store( T.Broadcast(T.float32(1), 4), [T.Ramp(i_0 * 4, 1, 4)], predicate=T.get_active_lane_mask("int1x4", i_0 * 4, 14), ) ``` Change-Id: I1305c1b5d052ad109232604c6660e40d4a566dd6

Change-Id: I8a893377d7361bed8840a645fbaff81ab401ccb8

Plumb this argument through the te.split implementation to achieve feature parity with tir.split. Change-Id: I92707bc08e857b9fd5678153d998aeecebcce228

ekalda · 2024-01-04T10:02:00Z

This prototype is to accompany the open SVE RFC. It implements the design outlined in the RFC.

The main changes to the stack include:

tir.split can accept an expression with vscale as a factor
LoopVectorizer can create Ramp and Broadcast nodes with scalable lanes
BufferLoad and BufferStore nodes can accept an optional predicate which is created in LoopVectorizer
LLVM codegen can lower the scalable predicated vectors into llvm.masked.* intrinsics

The prototype is currently missing tir.tile~~and TVMScript parser support for predicates~~.

cbalint13

One minor nit to the code part.

cbalint13 · 2024-01-04T13:42:02Z

tir.split can accept an expression with vscale as a factor
LoopVectorizer can create Ramp and Broadcast nodes with scalable lanes
BufferLoad and BufferStore nodes can accept an optional predicate which is created in LoopVectorizer
LLVM codegen can lower the scalable predicated vectors into llvm.masked.* intrinsics
The prototype is currently missing tir.tile and TVMScript parser support for predicates.

Hi @ekalda ,

Very nice work !

I can't comment much, I think this implementation is a careful step toward SVE.
Will test this on some RVV CPU implementation to see a walk through the LLVM masked.* things.

ekalda · 2024-01-10T10:30:45Z

@tvm-bot rerun

This prototype is to accompany the open SVE RFC. It implements the design outlined in the RFC. The main changes to the stack include: 1. tir.split can accept an expression with vscale as a factor 2. LoopVectorizer can create Ramp and Broadcast nodes with scalable lanes 3. BufferLoad and BufferStore nodes can accept an optional predicate which is created in LoopVectorizer 4. LLVM codegen can lower the scalable predicated vectors into llvm.masked.* intrinsics The prototype is currently missing tir.tile and TVMScript parser support for predicates. Co-authored-by: Luke Hutton <luke.hutton@arm.com> Co-authored-by: Neil Hickey <neil.hickey@arm.com>

Change-Id: I7d90c8b8396ba7a2b609a91bea2fe5f599d5cb96

Change-Id: I2e994ffdacaf1dacdc875c2cfd62be433e6952c6

This commit adds support for expressing and printing buffer loads/stores in TVMScript. The buffer API has been extended with load and store methods which support passing a predicate parameter to BufferLoad/Store. When the printer encounters a predicated BufferLoad/Store, it will print with the .load/.store syntax as opposed to the shorthand [...] syntax as it is easier to represent predicates. Extending the functionality of vload and vstore was considered but they do not currently support expressing loading/storing of non-consecutive values and such a change will result in many changes across the codebase. An example of a predicated load and store in TVMScript: ``` A.load( [T.Ramp(i_0 * 4, 1, 4)], predicate=T.get_active_lane_mask("int1x4", i_0 * 4, 14), ) B.store( T.Broadcast(T.float32(1), 4), [T.Ramp(i_0 * 4, 1, 4)], predicate=T.get_active_lane_mask("int1x4", i_0 * 4, 14), ) ``` Change-Id: I1305c1b5d052ad109232604c6660e40d4a566dd6

Change-Id: I8a893377d7361bed8840a645fbaff81ab401ccb8

Plumb this argument through the te.split implementation to achieve feature parity with tir.split. Change-Id: I92707bc08e857b9fd5678153d998aeecebcce228

ekalda · 2024-01-04T10:02:00Z

This prototype is to accompany the open SVE RFC. It implements the design outlined in the RFC.

The main changes to the stack include:

tir.split can accept an expression with vscale as a factor
LoopVectorizer can create Ramp and Broadcast nodes with scalable lanes
BufferLoad and BufferStore nodes can accept an optional predicate which is created in LoopVectorizer
LLVM codegen can lower the scalable predicated vectors into llvm.masked.* intrinsics

The prototype is currently missing tir.tile~~and TVMScript parser support for predicates~~.

cbalint13

One minor nit to the code part.

cbalint13 · 2024-01-04T13:42:02Z

tir.split can accept an expression with vscale as a factor
LoopVectorizer can create Ramp and Broadcast nodes with scalable lanes
BufferLoad and BufferStore nodes can accept an optional predicate which is created in LoopVectorizer
LLVM codegen can lower the scalable predicated vectors into llvm.masked.* intrinsics
The prototype is currently missing tir.tile and TVMScript parser support for predicates.

Hi @ekalda ,

Very nice work !

I can't comment much, I think this implementation is a careful step toward SVE.
Will test this on some RVV CPU implementation to see a walk through the LLVM masked.* things.

ekalda · 2024-01-10T10:30:45Z

@tvm-bot rerun

This prototype is to accompany the open SVE RFC. It implements the design outlined in the RFC. The main changes to the stack include: 1. tir.split can accept an expression with vscale as a factor 2. LoopVectorizer can create Ramp and Broadcast nodes with scalable lanes 3. BufferLoad and BufferStore nodes can accept an optional predicate which is created in LoopVectorizer 4. LLVM codegen can lower the scalable predicated vectors into llvm.masked.* intrinsics The prototype is currently missing tir.tile and TVMScript parser support for predicates. Co-authored-by: Luke Hutton <luke.hutton@arm.com> Co-authored-by: Neil Hickey <neil.hickey@arm.com>

Change-Id: I7d90c8b8396ba7a2b609a91bea2fe5f599d5cb96

Change-Id: I2e994ffdacaf1dacdc875c2cfd62be433e6952c6

This commit adds support for expressing and printing buffer loads/stores in TVMScript. The buffer API has been extended with load and store methods which support passing a predicate parameter to BufferLoad/Store. When the printer encounters a predicated BufferLoad/Store, it will print with the .load/.store syntax as opposed to the shorthand [...] syntax as it is easier to represent predicates. Extending the functionality of vload and vstore was considered but they do not currently support expressing loading/storing of non-consecutive values and such a change will result in many changes across the codebase. An example of a predicated load and store in TVMScript: ``` A.load( [T.Ramp(i_0 * 4, 1, 4)], predicate=T.get_active_lane_mask("int1x4", i_0 * 4, 14), ) B.store( T.Broadcast(T.float32(1), 4), [T.Ramp(i_0 * 4, 1, 4)], predicate=T.get_active_lane_mask("int1x4", i_0 * 4, 14), ) ``` Change-Id: I1305c1b5d052ad109232604c6660e40d4a566dd6

Change-Id: I8a893377d7361bed8840a645fbaff81ab401ccb8

Plumb this argument through the te.split implementation to achieve feature parity with tir.split. Change-Id: I92707bc08e857b9fd5678153d998aeecebcce228

ekalda · 2024-01-04T10:02:00Z

This prototype is to accompany the open SVE RFC. It implements the design outlined in the RFC.

The main changes to the stack include:

tir.split can accept an expression with vscale as a factor
LoopVectorizer can create Ramp and Broadcast nodes with scalable lanes
BufferLoad and BufferStore nodes can accept an optional predicate which is created in LoopVectorizer
LLVM codegen can lower the scalable predicated vectors into llvm.masked.* intrinsics

The prototype is currently missing tir.tile~~and TVMScript parser support for predicates~~.

cbalint13

One minor nit to the code part.

cbalint13 · 2024-01-04T13:42:02Z

tir.split can accept an expression with vscale as a factor
LoopVectorizer can create Ramp and Broadcast nodes with scalable lanes
BufferLoad and BufferStore nodes can accept an optional predicate which is created in LoopVectorizer
LLVM codegen can lower the scalable predicated vectors into llvm.masked.* intrinsics
The prototype is currently missing tir.tile and TVMScript parser support for predicates.

Hi @ekalda ,

Very nice work !

I can't comment much, I think this implementation is a careful step toward SVE.
Will test this on some RVV CPU implementation to see a walk through the LLVM masked.* things.

ekalda · 2024-01-10T10:30:45Z

@tvm-bot rerun

This prototype is to accompany the open SVE RFC. It implements the design outlined in the RFC. The main changes to the stack include: 1. tir.split can accept an expression with vscale as a factor 2. LoopVectorizer can create Ramp and Broadcast nodes with scalable lanes 3. BufferLoad and BufferStore nodes can accept an optional predicate which is created in LoopVectorizer 4. LLVM codegen can lower the scalable predicated vectors into llvm.masked.* intrinsics The prototype is currently missing tir.tile and TVMScript parser support for predicates. Co-authored-by: Luke Hutton <luke.hutton@arm.com> Co-authored-by: Neil Hickey <neil.hickey@arm.com>

Change-Id: I7d90c8b8396ba7a2b609a91bea2fe5f599d5cb96

Change-Id: I2e994ffdacaf1dacdc875c2cfd62be433e6952c6

This commit adds support for expressing and printing buffer loads/stores in TVMScript. The buffer API has been extended with load and store methods which support passing a predicate parameter to BufferLoad/Store. When the printer encounters a predicated BufferLoad/Store, it will print with the .load/.store syntax as opposed to the shorthand [...] syntax as it is easier to represent predicates. Extending the functionality of vload and vstore was considered but they do not currently support expressing loading/storing of non-consecutive values and such a change will result in many changes across the codebase. An example of a predicated load and store in TVMScript: ``` A.load( [T.Ramp(i_0 * 4, 1, 4)], predicate=T.get_active_lane_mask("int1x4", i_0 * 4, 14), ) B.store( T.Broadcast(T.float32(1), 4), [T.Ramp(i_0 * 4, 1, 4)], predicate=T.get_active_lane_mask("int1x4", i_0 * 4, 14), ) ``` Change-Id: I1305c1b5d052ad109232604c6660e40d4a566dd6

Change-Id: I8a893377d7361bed8840a645fbaff81ab401ccb8

Plumb this argument through the te.split implementation to achieve feature parity with tir.split. Change-Id: I92707bc08e857b9fd5678153d998aeecebcce228

ekalda · 2024-01-04T10:02:00Z

This prototype is to accompany the open SVE RFC. It implements the design outlined in the RFC.

The main changes to the stack include:

tir.split can accept an expression with vscale as a factor
LoopVectorizer can create Ramp and Broadcast nodes with scalable lanes
BufferLoad and BufferStore nodes can accept an optional predicate which is created in LoopVectorizer
LLVM codegen can lower the scalable predicated vectors into llvm.masked.* intrinsics

The prototype is currently missing tir.tile~~and TVMScript parser support for predicates~~.

cbalint13

One minor nit to the code part.

cbalint13 · 2024-01-04T13:42:02Z

tir.split can accept an expression with vscale as a factor
LoopVectorizer can create Ramp and Broadcast nodes with scalable lanes
BufferLoad and BufferStore nodes can accept an optional predicate which is created in LoopVectorizer
LLVM codegen can lower the scalable predicated vectors into llvm.masked.* intrinsics
The prototype is currently missing tir.tile and TVMScript parser support for predicates.

Hi @ekalda ,

Very nice work !

I can't comment much, I think this implementation is a careful step toward SVE.
Will test this on some RVV CPU implementation to see a walk through the LLVM masked.* things.

ekalda · 2024-01-10T10:30:45Z

@tvm-bot rerun

This prototype is to accompany the open SVE RFC. It implements the design outlined in the RFC. The main changes to the stack include: 1. tir.split can accept an expression with vscale as a factor 2. LoopVectorizer can create Ramp and Broadcast nodes with scalable lanes 3. BufferLoad and BufferStore nodes can accept an optional predicate which is created in LoopVectorizer 4. LLVM codegen can lower the scalable predicated vectors into llvm.masked.* intrinsics The prototype is currently missing tir.tile and TVMScript parser support for predicates. Co-authored-by: Luke Hutton <luke.hutton@arm.com> Co-authored-by: Neil Hickey <neil.hickey@arm.com>

Change-Id: I7d90c8b8396ba7a2b609a91bea2fe5f599d5cb96

Change-Id: I2e994ffdacaf1dacdc875c2cfd62be433e6952c6

This commit adds support for expressing and printing buffer loads/stores in TVMScript. The buffer API has been extended with load and store methods which support passing a predicate parameter to BufferLoad/Store. When the printer encounters a predicated BufferLoad/Store, it will print with the .load/.store syntax as opposed to the shorthand [...] syntax as it is easier to represent predicates. Extending the functionality of vload and vstore was considered but they do not currently support expressing loading/storing of non-consecutive values and such a change will result in many changes across the codebase. An example of a predicated load and store in TVMScript: ``` A.load( [T.Ramp(i_0 * 4, 1, 4)], predicate=T.get_active_lane_mask("int1x4", i_0 * 4, 14), ) B.store( T.Broadcast(T.float32(1), 4), [T.Ramp(i_0 * 4, 1, 4)], predicate=T.get_active_lane_mask("int1x4", i_0 * 4, 14), ) ``` Change-Id: I1305c1b5d052ad109232604c6660e40d4a566dd6

Change-Id: I8a893377d7361bed8840a645fbaff81ab401ccb8

Plumb this argument through the te.split implementation to achieve feature parity with tir.split. Change-Id: I92707bc08e857b9fd5678153d998aeecebcce228

ekalda · 2024-01-04T10:02:00Z

This prototype is to accompany the open SVE RFC. It implements the design outlined in the RFC.

The main changes to the stack include:

tir.split can accept an expression with vscale as a factor
LoopVectorizer can create Ramp and Broadcast nodes with scalable lanes
BufferLoad and BufferStore nodes can accept an optional predicate which is created in LoopVectorizer
LLVM codegen can lower the scalable predicated vectors into llvm.masked.* intrinsics

The prototype is currently missing tir.tile~~and TVMScript parser support for predicates~~.

cbalint13

One minor nit to the code part.

cbalint13 · 2024-01-04T13:42:02Z

tir.split can accept an expression with vscale as a factor
LoopVectorizer can create Ramp and Broadcast nodes with scalable lanes
BufferLoad and BufferStore nodes can accept an optional predicate which is created in LoopVectorizer
LLVM codegen can lower the scalable predicated vectors into llvm.masked.* intrinsics
The prototype is currently missing tir.tile and TVMScript parser support for predicates.

Hi @ekalda ,

Very nice work !

I can't comment much, I think this implementation is a careful step toward SVE.
Will test this on some RVV CPU implementation to see a walk through the LLVM masked.* things.

ekalda · 2024-01-10T10:30:45Z

@tvm-bot rerun

This prototype is to accompany the open SVE RFC. It implements the design outlined in the RFC. The main changes to the stack include: 1. tir.split can accept an expression with vscale as a factor 2. LoopVectorizer can create Ramp and Broadcast nodes with scalable lanes 3. BufferLoad and BufferStore nodes can accept an optional predicate which is created in LoopVectorizer 4. LLVM codegen can lower the scalable predicated vectors into llvm.masked.* intrinsics The prototype is currently missing tir.tile and TVMScript parser support for predicates. Co-authored-by: Luke Hutton <luke.hutton@arm.com> Co-authored-by: Neil Hickey <neil.hickey@arm.com>

Change-Id: I7d90c8b8396ba7a2b609a91bea2fe5f599d5cb96

Change-Id: I2e994ffdacaf1dacdc875c2cfd62be433e6952c6

This commit adds support for expressing and printing buffer loads/stores in TVMScript. The buffer API has been extended with load and store methods which support passing a predicate parameter to BufferLoad/Store. When the printer encounters a predicated BufferLoad/Store, it will print with the .load/.store syntax as opposed to the shorthand [...] syntax as it is easier to represent predicates. Extending the functionality of vload and vstore was considered but they do not currently support expressing loading/storing of non-consecutive values and such a change will result in many changes across the codebase. An example of a predicated load and store in TVMScript: ``` A.load( [T.Ramp(i_0 * 4, 1, 4)], predicate=T.get_active_lane_mask("int1x4", i_0 * 4, 14), ) B.store( T.Broadcast(T.float32(1), 4), [T.Ramp(i_0 * 4, 1, 4)], predicate=T.get_active_lane_mask("int1x4", i_0 * 4, 14), ) ``` Change-Id: I1305c1b5d052ad109232604c6660e40d4a566dd6

Change-Id: I8a893377d7361bed8840a645fbaff81ab401ccb8

Plumb this argument through the te.split implementation to achieve feature parity with tir.split. Change-Id: I92707bc08e857b9fd5678153d998aeecebcce228

ekalda mentioned this pull request Jan 4, 2024
[RFC] Scalable vectors in TIR apache/tvm-rfcs#104
Merged

cbalint13 requested changes Jan 4, 2024
View reviewed changes

Comment threadsrc/target/llvm/codegen_llvm.cc Outdated

ekalda force-pushed the vscale-in-tir branch from c5933da to 6fc5999Compare January 9, 2024 13:56

ekalda force-pushed the vscale-in-tir branch from 6fc5999 to 1a912fcCompare January 15, 2024 09:28

lhutton1 force-pushed the vscale-in-tir branch from 1a912fc to 134d6abCompare January 16, 2024 11:14

ekaldaand others added 6 commits January 22, 2024 09:23

Fix ci_gpu and ci_i386 builds
1a3c959
Change-Id: I7d90c8b8396ba7a2b609a91bea2fe5f599d5cb96

Fix i386 cpptest build
dd6ba3e
Change-Id: I2e994ffdacaf1dacdc875c2cfd62be433e6952c6

Skip codegen tests on i386 target
3a8c8e0
Change-Id: I8a893377d7361bed8840a645fbaff81ab401ccb8

Add support for disable_predication for te.split
c82f4c7
Plumb this argument through the te.split implementation to achieve feature parity with tir.split. Change-Id: I92707bc08e857b9fd5678153d998aeecebcce228

ekalda force-pushed the vscale-in-tir branch from 134d6ab to c82f4c7Compare January 22, 2024 10:08

tqchen closed this May 8, 2025

ekalda mentioned this pull request Jan 4, 2024
[RFC] Scalable vectors in TIR apache/tvm-rfcs#104
Merged

cbalint13 requested changes Jan 4, 2024
View reviewed changes

Comment threadsrc/target/llvm/codegen_llvm.cc Outdated

ekalda force-pushed the vscale-in-tir branch from c5933da to 6fc5999Compare January 9, 2024 13:56

ekalda force-pushed the vscale-in-tir branch from 6fc5999 to 1a912fcCompare January 15, 2024 09:28

lhutton1 force-pushed the vscale-in-tir branch from 1a912fc to 134d6abCompare January 16, 2024 11:14

ekaldaand others added 6 commits January 22, 2024 09:23

Fix ci_gpu and ci_i386 builds
1a3c959
Change-Id: I7d90c8b8396ba7a2b609a91bea2fe5f599d5cb96

Fix i386 cpptest build
dd6ba3e
Change-Id: I2e994ffdacaf1dacdc875c2cfd62be433e6952c6

Skip codegen tests on i386 target
3a8c8e0
Change-Id: I8a893377d7361bed8840a645fbaff81ab401ccb8

Add support for disable_predication for te.split
c82f4c7
Plumb this argument through the te.split implementation to achieve feature parity with tir.split. Change-Id: I92707bc08e857b9fd5678153d998aeecebcce228

ekalda force-pushed the vscale-in-tir branch from 134d6ab to c82f4c7Compare January 22, 2024 10:08

tqchen closed this May 8, 2025

ekalda mentioned this pull request Jan 4, 2024
[RFC] Scalable vectors in TIR apache/tvm-rfcs#104
Merged

cbalint13 requested changes Jan 4, 2024
View reviewed changes

Comment threadsrc/target/llvm/codegen_llvm.cc Outdated

ekalda force-pushed the vscale-in-tir branch from c5933da to 6fc5999Compare January 9, 2024 13:56

ekalda force-pushed the vscale-in-tir branch from 6fc5999 to 1a912fcCompare January 15, 2024 09:28

lhutton1 force-pushed the vscale-in-tir branch from 1a912fc to 134d6abCompare January 16, 2024 11:14

ekaldaand others added 6 commits January 22, 2024 09:23

Fix ci_gpu and ci_i386 builds
1a3c959
Change-Id: I7d90c8b8396ba7a2b609a91bea2fe5f599d5cb96

Fix i386 cpptest build
dd6ba3e
Change-Id: I2e994ffdacaf1dacdc875c2cfd62be433e6952c6

Skip codegen tests on i386 target
3a8c8e0
Change-Id: I8a893377d7361bed8840a645fbaff81ab401ccb8

Add support for disable_predication for te.split
c82f4c7
Plumb this argument through the te.split implementation to achieve feature parity with tir.split. Change-Id: I92707bc08e857b9fd5678153d998aeecebcce228

ekalda force-pushed the vscale-in-tir branch from 134d6ab to c82f4c7Compare January 22, 2024 10:08

tqchen closed this May 8, 2025

ekalda mentioned this pull request Jan 4, 2024
[RFC] Scalable vectors in TIR apache/tvm-rfcs#104
Merged

cbalint13 requested changes Jan 4, 2024
View reviewed changes

Comment threadsrc/target/llvm/codegen_llvm.cc Outdated

ekalda force-pushed the vscale-in-tir branch from c5933da to 6fc5999Compare January 9, 2024 13:56

ekalda force-pushed the vscale-in-tir branch from 6fc5999 to 1a912fcCompare January 15, 2024 09:28

lhutton1 force-pushed the vscale-in-tir branch from 1a912fc to 134d6abCompare January 16, 2024 11:14

ekaldaand others added 6 commits January 22, 2024 09:23

Fix ci_gpu and ci_i386 builds
1a3c959
Change-Id: I7d90c8b8396ba7a2b609a91bea2fe5f599d5cb96

Fix i386 cpptest build
dd6ba3e
Change-Id: I2e994ffdacaf1dacdc875c2cfd62be433e6952c6

Skip codegen tests on i386 target
3a8c8e0
Change-Id: I8a893377d7361bed8840a645fbaff81ab401ccb8

Add support for disable_predication for te.split
c82f4c7
Plumb this argument through the te.split implementation to achieve feature parity with tir.split. Change-Id: I92707bc08e857b9fd5678153d998aeecebcce228

ekalda force-pushed the vscale-in-tir branch from 134d6ab to c82f4c7Compare January 22, 2024 10:08

tqchen closed this May 8, 2025

ekalda mentioned this pull request Jan 4, 2024
[RFC] Scalable vectors in TIR apache/tvm-rfcs#104
Merged

cbalint13 requested changes Jan 4, 2024
View reviewed changes

Comment threadsrc/target/llvm/codegen_llvm.cc Outdated

ekalda force-pushed the vscale-in-tir branch from c5933da to 6fc5999Compare January 9, 2024 13:56

ekalda force-pushed the vscale-in-tir branch from 6fc5999 to 1a912fcCompare January 15, 2024 09:28

lhutton1 force-pushed the vscale-in-tir branch from 1a912fc to 134d6abCompare January 16, 2024 11:14

ekaldaand others added 6 commits January 22, 2024 09:23

Fix ci_gpu and ci_i386 builds
1a3c959
Change-Id: I7d90c8b8396ba7a2b609a91bea2fe5f599d5cb96

Fix i386 cpptest build
dd6ba3e
Change-Id: I2e994ffdacaf1dacdc875c2cfd62be433e6952c6

Skip codegen tests on i386 target
3a8c8e0
Change-Id: I8a893377d7361bed8840a645fbaff81ab401ccb8

Add support for disable_predication for te.split
c82f4c7
Plumb this argument through the te.split implementation to achieve feature parity with tir.split. Change-Id: I92707bc08e857b9fd5678153d998aeecebcce228

ekalda force-pushed the vscale-in-tir branch from 134d6ab to c82f4c7Compare January 22, 2024 10:08

tqchen closed this May 8, 2025

ekalda mentioned this pull request Jan 4, 2024
[RFC] Scalable vectors in TIR apache/tvm-rfcs#104
Merged

cbalint13 requested changes Jan 4, 2024
View reviewed changes

Comment threadsrc/target/llvm/codegen_llvm.cc Outdated

ekalda force-pushed the vscale-in-tir branch from c5933da to 6fc5999Compare January 9, 2024 13:56

ekalda force-pushed the vscale-in-tir branch from 6fc5999 to 1a912fcCompare January 15, 2024 09:28

lhutton1 force-pushed the vscale-in-tir branch from 1a912fc to 134d6abCompare January 16, 2024 11:14

ekaldaand others added 6 commits January 22, 2024 09:23

Fix ci_gpu and ci_i386 builds
1a3c959
Change-Id: I7d90c8b8396ba7a2b609a91bea2fe5f599d5cb96

Fix i386 cpptest build
dd6ba3e
Change-Id: I2e994ffdacaf1dacdc875c2cfd62be433e6952c6

Skip codegen tests on i386 target
3a8c8e0
Change-Id: I8a893377d7361bed8840a645fbaff81ab401ccb8

Add support for disable_predication for te.split
c82f4c7
Plumb this argument through the te.split implementation to achieve feature parity with tir.split. Change-Id: I92707bc08e857b9fd5678153d998aeecebcce228

ekalda force-pushed the vscale-in-tir branch from 134d6ab to c82f4c7Compare January 22, 2024 10:08

tqchen closed this May 8, 2025

ekalda mentioned this pull request Jan 4, 2024
[RFC] Scalable vectors in TIR apache/tvm-rfcs#104
Merged

cbalint13 requested changes Jan 4, 2024
View reviewed changes

Comment threadsrc/target/llvm/codegen_llvm.cc Outdated

ekalda force-pushed the vscale-in-tir branch from c5933da to 6fc5999Compare January 9, 2024 13:56

ekalda force-pushed the vscale-in-tir branch from 6fc5999 to 1a912fcCompare January 15, 2024 09:28

lhutton1 force-pushed the vscale-in-tir branch from 1a912fc to 134d6abCompare January 16, 2024 11:14

ekaldaand others added 6 commits January 22, 2024 09:23

Fix ci_gpu and ci_i386 builds
1a3c959
Change-Id: I7d90c8b8396ba7a2b609a91bea2fe5f599d5cb96

Fix i386 cpptest build
dd6ba3e
Change-Id: I2e994ffdacaf1dacdc875c2cfd62be433e6952c6

Skip codegen tests on i386 target
3a8c8e0
Change-Id: I8a893377d7361bed8840a645fbaff81ab401ccb8

Add support for disable_predication for te.split
c82f4c7
Plumb this argument through the te.split implementation to achieve feature parity with tir.split. Change-Id: I92707bc08e857b9fd5678153d998aeecebcce228

ekalda force-pushed the vscale-in-tir branch from 134d6ab to c82f4c7Compare January 22, 2024 10:08

tqchen closed this May 8, 2025

ekalda mentioned this pull request Jan 4, 2024
[RFC] Scalable vectors in TIR apache/tvm-rfcs#104
Merged

cbalint13 requested changes Jan 4, 2024
View reviewed changes

Comment threadsrc/target/llvm/codegen_llvm.cc Outdated

ekalda force-pushed the vscale-in-tir branch from c5933da to 6fc5999Compare January 9, 2024 13:56

ekalda force-pushed the vscale-in-tir branch from 6fc5999 to 1a912fcCompare January 15, 2024 09:28

lhutton1 force-pushed the vscale-in-tir branch from 1a912fc to 134d6abCompare January 16, 2024 11:14

ekaldaand others added 6 commits January 22, 2024 09:23

Fix ci_gpu and ci_i386 builds
1a3c959
Change-Id: I7d90c8b8396ba7a2b609a91bea2fe5f599d5cb96

Fix i386 cpptest build
dd6ba3e
Change-Id: I2e994ffdacaf1dacdc875c2cfd62be433e6952c6

Skip codegen tests on i386 target
3a8c8e0
Change-Id: I8a893377d7361bed8840a645fbaff81ab401ccb8

Add support for disable_predication for te.split
c82f4c7
Plumb this argument through the te.split implementation to achieve feature parity with tir.split. Change-Id: I92707bc08e857b9fd5678153d998aeecebcce228

ekalda force-pushed the vscale-in-tir branch from 134d6ab to c82f4c7Compare January 22, 2024 10:08

tqchen closed this May 8, 2025

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