Uh oh!
There was an error while loading. Please reload this page.
[SME][TOPI] Add conv2d NHWC SME fp32 schedule - #17003
Conversation
Anndrey24
commented
May 19, 2024
@tvm-bot rerun |
Failed to re-run CI in https://github.com/apache/tvm/actions/runs/9147913719 Detailswith response |
lhutton1
left a comment
There was a problem hiding this comment.
Thanks @Anndrey24 great work - it's awesome to see this coming together! I left a few comments, largely nitpicks and a couple of questions
Uh oh!
There was an error while loading. Please reload this page.
Uh oh!
There was an error while loading. Please reload this page.
Uh oh!
There was an error while loading. Please reload this page.
Uh oh!
There was an error while loading. Please reload this page.
Uh oh!
There was an error while loading. Please reload this page.
Uh oh!
There was an error while loading. Please reload this page.
Uh oh!
There was an error while loading. Please reload this page.
Uh oh!
There was an error while loading. Please reload this page.
Uh oh!
There was an error while loading. Please reload this page.
Uh oh!
There was an error while loading. Please reload this page.
This commit adds a scalable `arm_cpu` conv2d NHWC schedule for fp32 which generates SME instructions by using the tensor intrinsics introduced in apache#16921. Alongside the SME schedule, the logic of the TE schedule `schedule_conv2d_gemm_native()` for both non-scalable and scalable vector implementations has also been translated into the new TIR schedule. This means that the TE compute definition `compute_conv2d_NHWC_hybrid()` is now compatible with both the original TE schedules (e.g. `schedule_conv2d_NHWC_hybrid()`) and the newly introduced TIR schedule `schedule_conv2d_NHWC_hybrid_TIR()`. The corresponding TOPI test has been extended to reflect that.
Anndrey24
commented
May 28, 2024
Resolved the conflict! |
ekalda
commented
May 28, 2024
Thanks @Anndrey24 and @lhutton1, this is now merged! |
Thanks @Anndrey24@lhutton1@ekalda . Seems we have a breakage/flaky likely related to this pr https://ci.tlcpack.ai/blue/organizations/jenkins/tvm-arm/detail/main/1980/pipeline (in lint,arm, and cpu jobs). |
I created a temp revert, #17038 to unblock the ci, if there is an alternative fix that would also be good, eitherway we followup with a redo quickly. |
Fixes a merge conflict between apache#16981 and apache#17003. Change-Id: Ifcc983ef0b8c00250568a048fd682933adfdcde4
This commit adds a scalable
arm_cpuconv2d NHWC schedule for fp32 which generates SME instructions by using the tensor intrinsics introduced in #16921.Alongside the SME schedule, the logic of the TE schedule
schedule_conv2d_gemm_native()for both non-scalable and scalable vector implementations has also been translated into the new TIR schedule. This means that the TE compute definitioncompute_conv2d_NHWC_hybrid()is now compatible with both the original TE schedules (e.g.schedule_conv2d_NHWC_hybrid()) and the newly introduced TIR scheduleschedule_conv2d_NHWC_hybrid_TIR(). The corresponding TOPI test has been extended to reflect that.cc @ekalda@lhutton1