- 🔬 Passionate about Design Verification, Digital Design, and Computer Architecture
- 🧪 Hands-on experience with SystemVerilog, UVM, Verilog, and RTL Design
- 💻 Strong foundation in C++ and algorithmic problem solving
- 🚀 Currently deepening my skills in ASIC Verification and VLSI Design
- 🌱 Building projects that bridge hardware verification concepts with practical software problem-solving
- 🤖 Exploring AI/LLM systems — inference optimization, agentic architectures, and how models are deployed and scaled in production
Beyond hardware, I actively follow how modern AI systems are engineered and deployed:
Inference Optimization · KV Caching · Model Routing · Context Engineering · Harness Engineering · Autonomous Agents · Multi-Agent Systems · RAG (Retrieval-Augmented Generation) · MCP (Model Context Protocol) · Guardrails & AI Safety · Prompt Engineering
(SystemVerilog · UVM · Verilog · RTL Design)
