[ROCm] Preserve float bits in SIMT DPP reduction - #2089
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The AMD mov_dpp builtin operates on integer bits. Explicitly bitcast the floating-point accumulator before and after each lane move so older ROCm compilers do not emit numeric float-to-integer conversions. Add a gfx11 regression test covering the fused Linear4bit path for fp16, bf16, and fp32. Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>
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Summary
__builtin_amdgcn_mov_dpp.Linear4bitpath covering fp16,bf16, and fp32.
Fixes #2087.
Root cause
The HIP warp reduction passed a
floatdirectly to__builtin_amdgcn_mov_dpp. With ROCm 6.4.4 / clang 19, this produces numericfloat-to-integer and integer-to-float conversions around the DPP move instead
of moving the accumulator's IEEE-754 bits.
Explicit
__float_as_uint/__uint_as_floatconversions generate theexpected bit-preserving
v_mov_b32_dpp. This makes the intended operationindependent of compiler lowering and does not add a version-specific code
path.
ROCm 6.4.4 remains in the current bitsandbytes build matrix. A newer prebuilt
library passed the same numerical oracle, but the source should not rely on
compiler-dependent implicit conversions.
Validation
0.1252950.002051pre-commit run --all-files: passed.Only gfx1100 was physically tested. The exact affected ROCm 6.4 native library
was tested with torch 2.7.1 rather than the reporter's torch 2.9.1.
AI assistance was used for reproduction, diagnosis, and patch preparation. The
submitting human should review every changed line and the evidence before
publication.