ppcmmu: Ignore dcbz for MMIO regions

[mihaip]

The ATI drivers uses dcbz to simulate a write-combining buffer when sending HOST_DATA payloads.

The intent is something like this (on real hardware):

dcbz:
cache line = [0, 0, 0, 0, 0, 0, 0, 0]
ATI sees nothing
following stores:
cache line = [A, B, C, D, E, F, G, H]
ATI still sees nothing
dcbf or eviction:
write back [A, B, C, D, E, F, G, H]
ATI receives one completed cache line

With our cacheless implementation, the behavior was more like this:

dcbz:
ATI immediately receives [0, 0, 0, 0, 0, 0, 0, 0]
following stores:
ATI then receives [A, B, C, D, E, F, G, H]
dcbf:
no-op

The zero-ed out values have side effects (32 pixels of black being written), so the intermediate state was visible as visual corruption, especially visible when windows get redrawn on Mac OS 8.6.

The truly correct fix is to fully model the data cache, and do an eventual write back of the modified cache lines with their final values, but that is very invasive (and likely to be slow).

We instead just make dcbz a no-op for MMIO regions, which lets us avoid that intermediate state and unintended side effects.

[mihaip]

The ATI drivers uses dcbz to simulate a write-combining buffer when sending HOST_DATA payloads.

The intent is something like this (on real hardware):

dcbz:
cache line = [0, 0, 0, 0, 0, 0, 0, 0]
ATI sees nothing
following stores:
cache line = [A, B, C, D, E, F, G, H]
ATI still sees nothing
dcbf or eviction:
write back [A, B, C, D, E, F, G, H]
ATI receives one completed cache line

With our cacheless implementation, the behavior was more like this:

dcbz:
ATI immediately receives [0, 0, 0, 0, 0, 0, 0, 0]
following stores:
ATI then receives [A, B, C, D, E, F, G, H]
dcbf:
no-op

The zero-ed out values have side effects (32 pixels of black being written), so the intermediate state was visible as visual corruption, especially visible when windows get redrawn on Mac OS 8.6.

The truly correct fix is to fully model the data cache, and do an eventual write back of the modified cache lines with their final values, but that is very invasive (and likely to be slow).

We instead just make dcbz a no-op for MMIO regions, which lets us avoid that intermediate state and unintended side effects.

[mihaip]

The ATI drivers uses dcbz to simulate a write-combining buffer when sending HOST_DATA payloads.

The intent is something like this (on real hardware):

dcbz:
cache line = [0, 0, 0, 0, 0, 0, 0, 0]
ATI sees nothing
following stores:
cache line = [A, B, C, D, E, F, G, H]
ATI still sees nothing
dcbf or eviction:
write back [A, B, C, D, E, F, G, H]
ATI receives one completed cache line

With our cacheless implementation, the behavior was more like this:

dcbz:
ATI immediately receives [0, 0, 0, 0, 0, 0, 0, 0]
following stores:
ATI then receives [A, B, C, D, E, F, G, H]
dcbf:
no-op

The zero-ed out values have side effects (32 pixels of black being written), so the intermediate state was visible as visual corruption, especially visible when windows get redrawn on Mac OS 8.6.

The truly correct fix is to fully model the data cache, and do an eventual write back of the modified cache lines with their final values, but that is very invasive (and likely to be slow).

We instead just make dcbz a no-op for MMIO regions, which lets us avoid that intermediate state and unintended side effects.

[mihaip]

The ATI drivers uses dcbz to simulate a write-combining buffer when sending HOST_DATA payloads.

The intent is something like this (on real hardware):

dcbz:
cache line = [0, 0, 0, 0, 0, 0, 0, 0]
ATI sees nothing
following stores:
cache line = [A, B, C, D, E, F, G, H]
ATI still sees nothing
dcbf or eviction:
write back [A, B, C, D, E, F, G, H]
ATI receives one completed cache line

With our cacheless implementation, the behavior was more like this:

dcbz:
ATI immediately receives [0, 0, 0, 0, 0, 0, 0, 0]
following stores:
ATI then receives [A, B, C, D, E, F, G, H]
dcbf:
no-op

The zero-ed out values have side effects (32 pixels of black being written), so the intermediate state was visible as visual corruption, especially visible when windows get redrawn on Mac OS 8.6.

The truly correct fix is to fully model the data cache, and do an eventual write back of the modified cache lines with their final values, but that is very invasive (and likely to be slow).

We instead just make dcbz a no-op for MMIO regions, which lets us avoid that intermediate state and unintended side effects.

[mihaip]

The ATI drivers uses dcbz to simulate a write-combining buffer when sending HOST_DATA payloads.

The intent is something like this (on real hardware):

dcbz:
cache line = [0, 0, 0, 0, 0, 0, 0, 0]
ATI sees nothing
following stores:
cache line = [A, B, C, D, E, F, G, H]
ATI still sees nothing
dcbf or eviction:
write back [A, B, C, D, E, F, G, H]
ATI receives one completed cache line

With our cacheless implementation, the behavior was more like this:

dcbz:
ATI immediately receives [0, 0, 0, 0, 0, 0, 0, 0]
following stores:
ATI then receives [A, B, C, D, E, F, G, H]
dcbf:
no-op

The zero-ed out values have side effects (32 pixels of black being written), so the intermediate state was visible as visual corruption, especially visible when windows get redrawn on Mac OS 8.6.

The truly correct fix is to fully model the data cache, and do an eventual write back of the modified cache lines with their final values, but that is very invasive (and likely to be slow).

We instead just make dcbz a no-op for MMIO regions, which lets us avoid that intermediate state and unintended side effects.

[mihaip]

The ATI drivers uses dcbz to simulate a write-combining buffer when sending HOST_DATA payloads.

The intent is something like this (on real hardware):

dcbz:
cache line = [0, 0, 0, 0, 0, 0, 0, 0]
ATI sees nothing
following stores:
cache line = [A, B, C, D, E, F, G, H]
ATI still sees nothing
dcbf or eviction:
write back [A, B, C, D, E, F, G, H]
ATI receives one completed cache line

With our cacheless implementation, the behavior was more like this:

dcbz:
ATI immediately receives [0, 0, 0, 0, 0, 0, 0, 0]
following stores:
ATI then receives [A, B, C, D, E, F, G, H]
dcbf:
no-op

The zero-ed out values have side effects (32 pixels of black being written), so the intermediate state was visible as visual corruption, especially visible when windows get redrawn on Mac OS 8.6.

The truly correct fix is to fully model the data cache, and do an eventual write back of the modified cache lines with their final values, but that is very invasive (and likely to be slow).

We instead just make dcbz a no-op for MMIO regions, which lets us avoid that intermediate state and unintended side effects.

[mihaip]

The ATI drivers uses dcbz to simulate a write-combining buffer when sending HOST_DATA payloads.

The intent is something like this (on real hardware):

dcbz:
cache line = [0, 0, 0, 0, 0, 0, 0, 0]
ATI sees nothing
following stores:
cache line = [A, B, C, D, E, F, G, H]
ATI still sees nothing
dcbf or eviction:
write back [A, B, C, D, E, F, G, H]
ATI receives one completed cache line

With our cacheless implementation, the behavior was more like this:

dcbz:
ATI immediately receives [0, 0, 0, 0, 0, 0, 0, 0]
following stores:
ATI then receives [A, B, C, D, E, F, G, H]
dcbf:
no-op

The zero-ed out values have side effects (32 pixels of black being written), so the intermediate state was visible as visual corruption, especially visible when windows get redrawn on Mac OS 8.6.

The truly correct fix is to fully model the data cache, and do an eventual write back of the modified cache lines with their final values, but that is very invasive (and likely to be slow).

We instead just make dcbz a no-op for MMIO regions, which lets us avoid that intermediate state and unintended side effects.

[mihaip]

The ATI drivers uses dcbz to simulate a write-combining buffer when sending HOST_DATA payloads.

The intent is something like this (on real hardware):

dcbz:
cache line = [0, 0, 0, 0, 0, 0, 0, 0]
ATI sees nothing
following stores:
cache line = [A, B, C, D, E, F, G, H]
ATI still sees nothing
dcbf or eviction:
write back [A, B, C, D, E, F, G, H]
ATI receives one completed cache line

With our cacheless implementation, the behavior was more like this:

dcbz:
ATI immediately receives [0, 0, 0, 0, 0, 0, 0, 0]
following stores:
ATI then receives [A, B, C, D, E, F, G, H]
dcbf:
no-op

The zero-ed out values have side effects (32 pixels of black being written), so the intermediate state was visible as visual corruption, especially visible when windows get redrawn on Mac OS 8.6.

The truly correct fix is to fully model the data cache, and do an eventual write back of the modified cache lines with their final values, but that is very invasive (and likely to be slow).

We instead just make dcbz a no-op for MMIO regions, which lets us avoid that intermediate state and unintended side effects.