[Arm64] Load one single-element structure and Replicate to all lanes of one register

[echesakov]

class AdvSimd.Arm64
{
 /// <summary>
 /// float64x2_t vld1q_dup_f64 (float64_t const * ptr)
 /// A64: LD1R { Vt.2D }, [Xn]
 /// </summary>
 public static unsafe Vector128<double> LoadAndReplicateToVector128(double* address) => LoadAndReplicateToVector128(address);

 /// <summary>
 /// int64x2_t vld1q_dup_s64 (int64_t const * ptr)
 /// A64: LD1R { Vt.2D }, [Xn]
 /// </summary>
 public static unsafe Vector128<long> LoadAndReplicateToVector128(long* address) => LoadAndReplicateToVector128(address);

 /// <summary>
 /// uint64x2_t vld1q_dup_u64 (uint64_t const * ptr)
 /// A64: LD1R { Vt.2D }, [Xn]
 /// </summary>
 public static unsafe Vector128<ulong> LoadAndReplicateToVector128(ulong* address) => LoadAndReplicateToVector128(address);
}
class AdvSimd
{
 /// <summary>
 /// uint8x8_t vld1_dup_u8 (uint8_t const * ptr)
 /// A32: VLD1.8 { Dd[] }, [Rn]
 /// A64: LD1R { Vt.8B }, [Xn]
 /// </summary>
 public static unsafe Vector64<byte> LoadAndReplicateToVector64(byte* address) => LoadAndReplicateToVector64(address);

 /// <summary>
 /// int16x4_t vld1_dup_s16 (int16_t const * ptr)
 /// A32: VLD1.16 { Dd[] }, [Rn]
 /// A64: LD1R { Vt.4H }, [Xn]
 /// </summary>
 public static unsafe Vector64<short> LoadAndReplicateToVector64(short* address) => LoadAndReplicateToVector64(address);

 /// <summary>
 /// int32x2_t vld1_dup_s32 (int32_t const * ptr)
 /// A32: VLD1.32 { Dd[] }, [Rn]
 /// A64: LD1R { Vt.2S }, [Xn]
 /// </summary>
 public static unsafe Vector64<int> LoadAndReplicateToVector64(int* address) => LoadAndReplicateToVector64(address);

 /// <summary>
 /// int8x8_t vld1_dup_s8 (int8_t const * ptr)
 /// A32: VLD1.8 { Dd[] }, [Rn]
 /// A64: LD1R { Vt.8B }, [Xn]
 /// </summary>
 public static unsafe Vector64<sbyte> LoadAndReplicateToVector64(sbyte* address) => LoadAndReplicateToVector64(address);

 /// <summary>
 /// float32x2_t vld1_dup_f32 (float32_t const * ptr)
 /// A32: VLD1.32 { Dd[] }, [Rn]
 /// A64: LD1R { Vt.2S }, [Xn]
 /// </summary>
 public static unsafe Vector64<float> LoadAndReplicateToVector64(float* address) => LoadAndReplicateToVector64(address);

 /// <summary>
 /// uint16x4_t vld1_dup_u16 (uint16_t const * ptr)
 /// A32: VLD1.16 { Dd[] }, [Rn]
 /// A64: LD1R { Vt.4H }, [Xn]
 /// </summary>
 public static unsafe Vector64<ushort> LoadAndReplicateToVector64(ushort* address) => LoadAndReplicateToVector64(address);

 /// <summary>
 /// uint32x2_t vld1_dup_u32 (uint32_t const * ptr)
 /// A32: VLD1.32 { Dd[] }, [Rn]
 /// A64: LD1R { Vt.2S }, [Xn]
 /// </summary>
 public static unsafe Vector64<uint> LoadAndReplicateToVector64(uint* address) => LoadAndReplicateToVector64(address);

 /// <summary>
 /// uint8x16_t vld1q_dup_u8 (uint8_t const * ptr)
 /// A32: VLD1.8 { Dd[], Dd+1[] }, [Rn]
 /// A64: LD1R { Vt.16B }, [Xn]
 /// </summary>
 public static unsafe Vector128<byte> LoadAndReplicateToVector128(byte* address) => LoadAndReplicateToVector128(address);

 /// <summary>
 /// int16x8_t vld1q_dup_s16 (int16_t const * ptr)
 /// A32: VLD1.16 { Dd[], Dd+1[] }, [Rn]
 /// A64: LD1R { Vt.8H }, [Xn]
 /// </summary>
 public static unsafe Vector128<short> LoadAndReplicateToVector128(short* address) => LoadAndReplicateToVector128(address);

 /// <summary>
 /// int32x4_t vld1q_dup_s32 (int32_t const * ptr)
 /// A32: VLD1.32 { Dd[], Dd+1[] }, [Rn]
 /// A64: LD1R { Vt.4S }, [Xn]
 /// </summary>
 public static unsafe Vector128<int> LoadAndReplicateToVector128(int* address) => LoadAndReplicateToVector128(address);

 /// <summary>
 /// int8x16_t vld1q_dup_s8 (int8_t const * ptr)
 /// A32: VLD1.8 { Dd[], Dd+1[] }, [Rn]
 /// A64: LD1R { Vt.16B }, [Xn]
 /// </summary>
 public static unsafe Vector128<sbyte> LoadAndReplicateToVector128(sbyte* address) => LoadAndReplicateToVector128(address);

 /// <summary>
 /// float32x4_t vld1q_dup_f32 (float32_t const * ptr)
 /// A32: VLD1.32 { Dd[], Dd+1[] }, [Rn]
 /// A64: LD1R { Vt.4S }, [Xn]
 /// </summary>
 public static unsafe Vector128<float> LoadAndReplicateToVector128(float* address) => LoadAndReplicateToVector128(address);

 /// <summary>
 /// uint16x8_t vld1q_dup_u16 (uint16_t const * ptr)
 /// A32: VLD1.16 { Dd[], Dd+1[] }, [Rn]
 /// A64: LD1R { Vt.8H }, [Xn]
 /// </summary>
 public static unsafe Vector128<ushort> LoadAndReplicateToVector128(ushort* address) => LoadAndReplicateToVector128(address);

 /// <summary>
 /// uint32x4_t vld1q_dup_u32 (uint32_t const * ptr)
 /// A32: VLD1.32 { Dd[], Dd+1[] }, [Rn]
 /// A64: LD1R { Vt.4S }, [Xn]
 /// </summary>
 public static unsafe Vector128<uint> LoadAndReplicateToVector128(uint* address) => LoadAndReplicateToVector128(address);
}

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[echesakov]

@CarolEidt, @tannergooding , @TamarChristinaArm PTAL

[echesakov]

@TamarChristinaArm It looks that there is an error on https://developer.arm.com/architectures/instruction-sets/simd-isas/neon/intrinsics?search=ld1r - the website said that int64x2_t vld1q_dup_s64 (int64_t const * ptr) and uint64x2_t vld1q_dup_u64 (uint64_t const * ptr) are supported on v7/A32/A64. However, Arm Architecture Reference Manual says that VLD1 (single element to all lanes) instruction supports only .8 .16 and .32 element sizes.

I assumed that the latter is more accurate, so I put Vector128<long>, Vector128<ulong> and Vector128<double> variants into AdmSimd.Arm64 class.

[tannergooding]

@echesakovMSFT, Do you think this should be called LoadScalar... to clarify that the T* only loads a single T from memory?

[tannergooding]

For x86, we call this BroadcastScalarToVector128, so maybe ReplicateScalarToVector128 would be an alternative name on the ARM side (dropping LoadAnd)...

[echesakov]

@echesakovMSFT, Do you think this should be called LoadScalar... to clarify that the T* only loads a single T from memory?

There are LD2R, LD3R and LD4R that load 2, 3 and 4 Ts from the memory. Wouldn't we want to expose them via the same method name? This is under assumption that we will support Vector128x{n}<T> in the future

[echesakov]

For x86, we call this BroadcastScalarToVector128, so maybe ReplicateScalarToVector128 would be an alternative name on the ARM side (dropping LoadAnd)...

Yep, ReplicateScalarToVector128 was my first choice but then I switched to LoadAndReplicateToVector128 for above-mentioned reasons

[tannergooding]

I don't think we can expose them with the same name due to overload resolution....

Do we have some idea for names/shape of the LD2, LD3, and LD4 methods yet? Functionally, they are effectively:

(Vector128<T>) LD1R((T)* address);
(Vector128<T>, Vector128<T>) LD2R((T, T)* address);
(Vector128<T>, Vector128<T>, Vector128<T>) LD3R((T, T, T)* address);
(Vector128<T>, Vector128<T>, Vector128<T>, Vector128<T>) LD4R((T, T, T, T)* address);

As for shape, we would need to determine if we use Vector128<T>* for the results or if we use value tuples (so far, all HWIntrinsic APIs that have returned multiple values have used the former).
We would also need to determine how to encode the address; and while I'd be okay with returning a value tuple; I don't think taking a tuple as the address would be very good (for multiple reasons).
I don't think we'd want to take a value tuple in as the pointer however

[echesakov]

Can we have a separate structure that represents n consecutive SIMD registers? Something like Vector64x2<T>. Then these becomes easier

Vector64x2<uint> LoadAndReplicateToVector64x2(uint* address)

I don't think that we need a pointer to anything other than primitive types here.

[echesakov]

I think this is what you proposed here #24790 (comment)