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[RISC-V] Add pseudoinstructions to disassembler - #102260
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This reverts commit a011c43.
Tagging subscribers to this area: @JulieLeeMSFT, @jakobbotsch |
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clamp03
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LGTM
Did you check coreclr test? Could you show some dump examples?
Bajtazar
commented
May 16, 2024
Tests passes fine Examples of disassm:
Prior slli a2, a2,7 addi a2, a2,0 ld a2,0(a2)New slli a2, a2,7 mv a2, a2 ld a2,0(a2)
Prior G_M10072_IG07: ;; offset=0x0064 sltiu a0, s1,65 slli a0, a0,56 srli a0, a0,56 addiw t6, a0,0 bne t6, zero, G_M10072_IG11 jal zero,80New G_M10072_IG07: ;; offset=0x0064 sltiu a0, s1,65 slli a0, a0,56 srli a0, a0,56 addiw t6, a0,0 bnez t6, G_M10072_IG11 j 80
Prior G_M55990_IG31: ;; offset=0x1578 addi zero, zero,0New G_M55990_IG31: ;; offset=0x1578nop |
clamp03
commented
May 21, 2024
@tomeksowi@jakobbotsch@jkotas Could you review this PR? |
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risc-vv
commented
May 23, 2024
RISC-V test results for qemu-prio0-checked: 2718 / 2738 (99.27%)detailsGIT: 6869460 failed testskilled testsskipped tests |
risc-vv
commented
May 23, 2024
RISC-V test results for starfive-prio0-checked: 2720 / 2738 (99.34%)detailsGIT: 6869460 failed testskilled testsskipped tests |
risc-vv
commented
May 23, 2024
RISC-V test results for qemu-prio1-checked: 9396 / 9443 (99.50%)detailsGIT: 6869460 failed testskilled testsskipped tests |
risc-vv
commented
May 23, 2024
RISC-V test results for starfive-prio1-checked: 9399 / 9443 (99.53%)detailsGIT: 6869460 failed testskilled testsskipped tests |
jakobbotsch
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Can you please fix the conflicts?
risc-vv
commented
May 28, 2024
RISC-V testing failed on init-builddetailsGIT: a4381bd Cloning into 'runtime'...
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Switched to a new branch 'build-net'
Checking patch src/coreclr/jit/emitriscv64.cpp...
Hunk #1 succeeded at 3506 (offset 3 lines).
Checking patch src/coreclr/jit/emitriscv64.cpp...
Hunk #1 succeeded at 3506 (offset 3 lines).
Hunk #2 succeeded at 3555 (offset 3 lines).
Checking patch src/coreclr/jit/emitriscv64.cpp...
Hunk #1 succeeded at 3508 (offset 3 lines).
Hunk #2 succeeded at 3532 (offset 3 lines).
Checking patch src/coreclr/jit/emitriscv64.cpp...
Hunk #1 succeeded at 3508 (offset 3 lines).
Hunk #2 succeeded at 3570 (offset 3 lines).
Checking patch src/coreclr/jit/emitriscv64.cpp...
Hunk #1 succeeded at 3347 (offset 3 lines).
Hunk #2 succeeded at 3413 (offset 3 lines).
Hunk #3 succeeded at 3822 (offset 10 lines).
Checking patch src/coreclr/jit/emitriscv64.h...
Checking patch src/coreclr/jit/emitriscv64.cpp...
Hunk #1 succeeded at 3825 (offset 10 lines).
Checking patch src/coreclr/jit/emitriscv64.cpp...
Hunk #1 succeeded at 3347 (offset 3 lines).
Hunk #2 succeeded at 3367 (offset 3 lines).
Hunk #3 succeeded at 3457 (offset 3 lines).
Checking patch src/coreclr/jit/emitriscv64.cpp...
Hunk #1 succeeded at 3478 (offset 3 lines).
Hunk #2 succeeded at 3516 (offset 3 lines).
Hunk #3 succeeded at 3822 (offset 10 lines).
Hunk #4 succeeded at 3901 (offset 10 lines).
Checking patch src/coreclr/jit/emitriscv64.cpp...
Hunk #1 succeeded at 3428 (offset 3 lines).
Hunk #2 succeeded at 3531 (offset 3 lines).
Hunk #3 succeeded at 3908 (offset 10 lines).
Checking patch src/coreclr/jit/codegenriscv64.cpp...
Checking patch src/coreclr/jit/emitriscv64.cpp...
error: while searching for:
{
code_t code = emitInsCode(ins);if (INS_mov == ins)
{
assert(isGeneralRegisterOrR0(reg1));
assert(isGeneralRegisterOrR0(reg2));
error: patch failed: src/coreclr/jit/emitriscv64.cpp:588
error: src/coreclr/jit/emitriscv64.cpp: patch does not apply
Checking patch src/coreclr/jit/instrsriscv64.h...
error: while searching for:
INST(nop, "nop", 0, 0x00000013)
//// R_R
INST(mov, "mov", 0, 0x00000013)
////R_I
INST(lui, "lui", 0, 0x00000037)
error: patch failed: src/coreclr/jit/instrsriscv64.h:35
error: src/coreclr/jit/instrsriscv64.h: patch does not apply
Checking patch src/coreclr/jit/codegenriscv64.cpp...
Checking patch src/coreclr/jit/emitriscv64.cpp...
error: while searching for:
inline bool emitter::emitInsMayWriteToGCReg(instruction ins)
{
assert(ins != INS_invalid);return (ins <= INS_remuw) && (ins >= INS_mv) &&!(ins >= INS_jal && ins <= INS_bgeu && ins != INS_jalr) &&
(CodeGenInterface::instInfo[ins] & ST) == 0
?true:false;
error: patch failed: src/coreclr/jit/emitriscv64.cpp:141
error: src/coreclr/jit/emitriscv64.cpp: patch does not apply
Checking patch src/coreclr/jit/instrsriscv64.h...
error: while searching for:
INST(nop, "nop", 0, 0x00000013)
//// R_R
INST(mv, "mv", 0, 0x00000013)
////R_I
INST(lui, "lui", 0, 0x00000037)
error: patch failed: src/coreclr/jit/instrsriscv64.h:35
error: src/coreclr/jit/instrsriscv64.h: patch does not apply
Checking patch src/coreclr/jit/instrsriscv64.h...
error: while searching for:
INST(nop, "nop", 0, 0x00000013)
//// R_R
INST(mov, "mov", 0, 0x00000013)
////R_I
INST(lui, "lui", 0, 0x00000037)
error: patch failed: src/coreclr/jit/instrsriscv64.h:35
error: src/coreclr/jit/instrsriscv64.h: patch does not apply
Checking patch src/coreclr/jit/emitriscv64.cpp...
Hunk #1 succeeded at 3360 (offset 3 lines).
Hunk #2 succeeded at 3373 (offset 3 lines).
Hunk #3 succeeded at 3524 (offset 3 lines).
Checking patch src/coreclr/jit/emitriscv64.cpp...
Hunk #1 succeeded at 3540 (offset 3 lines).
Hunk #2 succeeded at 3562 (offset 3 lines).
Hunk #3 succeeded at 3587 (offset 3 lines).
Checking patch src/coreclr/jit/emitriscv64.cpp...
error: while searching for:
case 0x0: // ADDIW
printf("addiw %s, %s, %d\n", rd, rs1, imm12);return;case 0x1: // SLLIW
printf("slliw %s, %s, %d\n", rd, rs1, imm12 & 0x3f); // 6 BITS forSHAMTin RISCV64
return;case 0x5: // SRLIW & SRAIW
if(((code >>30) &0x1) ==0) { printf("srliw %s, %s, %d\n", rd, rs1, imm12 & 0x1f); // 5BITS for SHAMT in RISCV64 } else { printf("sraiw %s, %s, %d\n", rd, rs1, imm12 & 0x1f); // 5BITS for SHAMT in RISCV64 } return; default: printf("RISCV64 illegal instruction: 0x%08X\n", code); return; } } case 0x33:error: patch failed: src/coreclr/jit/emitriscv64.cpp:3614error: src/coreclr/jit/emitriscv64.cpp: patch does not applyChecking patch src/coreclr/jit/emitriscv64.cpp...error: while searching for: case 0x5: // SRLIW & SRAIW { static constexpr unsigned kLogicalShiftFunct7 = 0x00; static constexpr unsigned kArithmeticShiftFunct7 = 0x30; unsigned funct7 = (imm12 >> 5) & 0x7f; if (funct7 == kLogicalShiftFunct7)error: patch failed: src/coreclr/jit/emitriscv64.cpp:3631error: src/coreclr/jit/emitriscv64.cpp: patch does not applyChecking patch src/coreclr/jit/emitriscv64.cpp...error: while searching for: case 0x1: // SLLIW { unsigned funct7 = (imm12 >> 5) & 0x7f; // SLLI's instruction code's upper 7 bits have to be equal to zero if (funct7 == 0) { printf("slliw %s, %s, %d\n", rd, rs1, imm12 & 0x1f); // 5 BITS for SHAMT in RISCV64error: patch failed: src/coreclr/jit/emitriscv64.cpp:3617error: src/coreclr/jit/emitriscv64.cpp: patch does not applyChecking patch src/coreclr/jit/emitriscv64.cpp...Hunk #1 succeeded at 3563 (offset 3 lines).error: while searching for: return; case 0x5: // SRLIW & SRAIW { static constexpr unsigned kLogicalShiftFunct7 = 0x00; static constexpr unsigned kArithmeticShiftFunct7 = 0x20; unsigned funct7 = (imm12 >> 5) & 0x7f; if (funct7 == kLogicalShiftFunct7)error: patch failed: src/coreclr/jit/emitriscv64.cpp:3630error: src/coreclr/jit/emitriscv64.cpp: patch does not applyChecking patch src/coreclr/jit/emitriscv64.cpp...Hunk #1 succeeded at 3541 (offset 3 lines).error: while searching for: return; case 0x1: // SLLIW { unsigned funct7 = (imm12 >> 5) & 0x7f; // SLLIW's instruction code's upper 7 bits have to be equal to zero if (funct7 == 0) { printf("slliw %s, %s, %d\n", rd, rs1, imm12 & 0x1f); // 5 BITS for SHAMT in RISCV64 }error: patch failed: src/coreclr/jit/emitriscv64.cpp:3616error: src/coreclr/jit/emitriscv64.cpp: patch does not applyChecking patch src/coreclr/jit/emitriscv64.cpp...Hunk #1 succeeded at 3644 (offset -14 lines).Checking patch src/coreclr/jit/emitriscv64.cpp...Hunk #1 succeeded at 3733 (offset -14 lines).Checking patch src/coreclr/jit/emitriscv64.cpp...error: while searching for: break; case 0x1: // SLLI { static constexpr kSlliFunct6 = 0b000000; unsigned funct6 = (imm12 >> 6) & 0x3f; // SLLI's instruction code's upper 6 bits have to be equal to zeroerror: patch failed: src/coreclr/jit/emitriscv64.cpp:3538error: src/coreclr/jit/emitriscv64.cpp: patch does not applyChecking patch src/coreclr/jit/emitriscv64.cpp...error: while searching for: switch (opcode3) { case 0x0: // ADDW return; return; case 0x1: // SLLW printf("sllw %s, %s, %s\n", rd, rs1, rs2); return; case 0x5: // SRLW { return; default: return emitDispIllegalInstruction(code);error: patch failed: src/coreclr/jit/emitriscv64.cpp:3759error: src/coreclr/jit/emitriscv64.cpp: patch does not applyChecking patch src/coreclr/jit/emitriscv64.cpp...Hunk #1 succeeded at 3591 (offset 1 line). |
Bajtazar
commented
May 29, 2024
Conflicts have been fixed. Could you please review new changes? |
* [RISC-V] Reworked emitDispInsName a bit to ease further development * [RISC-V] Little improvements * [RISC-V] Refactored code * [RISC-V] Added mv and nop pseudoinstructions to disasm * [RISC-V] Added branch pseudos to disasm * [RISC-V] Removed dead code * [RISC-V] Fixes * [RISC-V] Added j pseudoinstruction to disasm * [RISC-V] Improved readability * [RISC-V] Fixed mov pseudoinstruction * Revert "[RISC-V] Fixed mov pseudoinstruction" This reverts commit a011c43. * [RISC-V] Fixed mov printing name * [RISC-V] After review changes * [RISC-V] More fixes after review * [RISC-V] Adjusted 32-bit shift disasm to changes * [RISC-V] Fixed bug * [RISC-V] Fixed comment * [RISC-V] Changed constants' literal type * [RISC-V] Added more constants * [RISC-V] Reinforced printing 1 * [RISC-V] Reinforced printing 2 * [RISC-V] Fixed bug * [RISC-V] Resolved more bugs * [RISC-V] Removed dead assert
Adds pseudoinstruction printing to the disassembler. Requested in #102074 (comment)
Part of #84834, cc @dotnet/samsung